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402 13 THE PC TIMER

TIMER 1

Timer 1 is used to generate a periodic signal for driving the hardware that refreshes the dynamic RAM (memory). Timer 1 also has its clock and gate signals permanently wired. Like Timer 0, it has an output latch register that allows software to read the count value. The state of its output signal can be determined by reading Timer 1’s status register.

TIMER 2

Timer 2 is used to drive the speaker via an AND gate whose other input is programmable (see Figure 13-1). Its clock signal is permanently connected, although the gate is free to be controlled through software. Timer 2 also has an output latch register that allows software to read the count value. Similarly, the state of its output signal can be determined by reading Timer 2’s status register.

13.2.1 Configuring the Counters

As mentioned earlier, all three timers countdown when operating. The number loaded into each timer’s counter determines the timing duration. Therefore, writing a smaller number to a counter will result in a shorter time interval before it reaches zero. A particular counter can be read or written to at any time.

The counter’s value is constantly changing as it operates and can be read by sampling the count value and storing the result. The hardware device that performs such a function is known as a latch register. Each timer has an input latch register to allow writes to its counter (load it) and also an output latch register to allow its counter’s value to be read. This event is also dependent upon the status of the gate and the mode of operation.

A special Control Register is used to provide the facility to select which counter we wish to write to or read from, set the mode of operation, set the number format, etc. There is one more register in addition to the three Timer registers and the Control Register. This register allows access to the output of Timer 2 and the speaker gate control signal.

Timer Ports

Table 13-1 Port addresses - PC timers and speakers.

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The timers are part of your hardware system. To be able to program the timers, software must have access to timer subsystem hardware. This is possible by accessing the timer’s ports similar to the way we accessed the parallel port hardware using its port addresses. The port addresses associated with the timer and speaker system are given in Table 13-1.

Programming the timer starts with programming the Control Register as described in the following sections.

13.2.2 The Control Register

The Control Register is used to configure a timer. It can also be used to request the counter status or to latch the current count value. The register contains eight bits that must be appropriately set to enable the following:

The configuration of the Control Register is shown in Table 13-2.

Table 13-2 Configuration of the Control Register (address 0x43).

Select Counter

The counter can be selected by programming Bits 6 (SC0) and 7 (SC1) of the Control Register as shown:

01 Counter 1

10 Counter 2

Byte(s) used to Read/Load Counters

Bits 4 (RL0) and 5 (RL1) can be programmed to choose either Least Significant Byte (LSB) only, or the Most Significant Byte (MSB) only, or to use both bytes of the counter when counting:

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For example; if the LSB is to be written to a counter, RL1 and RL0 will need to be set at 0 and 1 respectively. The LSB is then loaded into the counter by writing to its data register (e.g. 0x40 for Timer 0).

If the MSB is to be written to a counter, RL1 and RL0 will need to be set to 1 and 0 respectively. The MSB is then loaded into the counter by writing to its data register (e.g. 0x40 for Timer 0).

If a 16-bit number (two bytes) is to be written to a counter, both RL1 and RL0 will need to be set to 1. The 16-bit number will be loaded into the counter by carrying out two consecutive write operations to the appropriate data register (e.g. 0x40 for Timer 0) by first writing the LSB followed by writing the MSB.

Counting format (Binary/BCD)

The mode of counting can be set to binary (typically used) or BCD (Binary Coded Decimal) - we don’t explain counting in BCD mode, so set the bit to 0.

Timer mode of operation

Mode Select

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The Timer’s modes of operation are explained in the next section. They are set using the Control Register bits 1, 2 and 3 as shown in the previous table.

13.2.3 Modes of Operation of the Timers

There are up to six different modes of timer operation. Timer 0 and Timer 1 have their gates hard-wired to a logic-HIGH level. This excludes them from operating in some of the modes described below. Timer 2 is the only timer that has a controllable gate. As such it can operate in all six modes.

Count

Time

Mode 0: Single Timeout

In this mode, the counter generates a low-level output signal for the fixed number of clock pulses loaded into its data register. Each incoming clock pulse will decrement the count value by one count (provided the gate input is high). When the count value reaches 0, the output line will change from low to remain high. Note that the maximum period is obtained when the decimal number 65,535 is loaded into the counter. This period will be approximately 54.9 ms.

All three counters can be programmed in this mode. To initiate single timeout operation, first configure the timer to operate in this mode and then write the count value to the data register. The countdown will begin immediately after writing the count data. If the gate signal is held low, counting stops until the gate signal returns high. Timers 0 and 1 have their gate signals hard-wired to a logic-HIGH level. This is not the case for Timer 2, whose gate input can be controlled by writing to bit 0 of the port 0x61. The bits of the port at 0x61 for operating Timer 2 are shown in Table 13-3.

Table 13-3 Bits at port address 0x61 (control of Timer 2 output & speaker).

Mode 1: Re-triggerable one-shot

This mode is used to generate a low-level pulse following a trigger command from the gate (hence only Timer 2 can use this mode). The duration of the pulse is set by the count value loaded into the counter. The gate signal is briefly sent from low to high and back to low to initiate counting down. As this happens, the counter output will drop from a high state to a low state. When the count value has decremented to zero, the output will return to a high state.

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The previously used count value is automatically reloaded into the counter at the end of the countdown when the counter reaches zero. Another one-shot period is generated when another high pulse is applied to the gate (hence the term ‘retriggerable’). The timer can also be re-triggered during the current countdown. In this case, a new countdown will start immediately after the re-trigger. A new count value can also be written to the input latch register during the current countdown; this will not affect the current countdown. The new count value in the input latch register will be loaded for the next countdown immediately after the next retrigger.

Count Count

Time Time

Mode 2: Rate generator

This mode is used to periodically generate a narrow low-level output pulse. When the value that was loaded into the counter reaches 1, the output changes to a low state for one clock period. The count value is then automatically reloaded to repeat the same process. All three timers can be used in this mode. Counting is stopped whenever the gate signal is low (only applies to Timer 2). The rate generator is predominantly used to generate hardware interrupts at regular intervals since the narrow pulse can be missed when detecting using software means.

Mode 3: Square wave generator

This mode produces a continuous square wave output. Everytime the timer’s counter reaches zero, the output toggles and the count value is automatically reloaded into the counter from its input latch. Note that the gate must be high to enable down-counting and the count is decremented by two for each clock pulse. All three timers can operate in this mode. Timer 0 generates the timer interrupt when configured in this mode.

Count

Time

Mode 4: Software triggered strobe

Counting down is initiated when a count value is written to the data register. This mode produces a single narrow output pulse for one clock period when the count reaches zero (a non-periodic narrow pulse is known as a strobe). The counter will remain inactive until at a later time software again writes to the counter. The gate must be high at all times to enable operation.

Count

Time

Mode 5: Hardware triggered strobe

This mode is identical to Mode 4 except triggering is carried out by hardware means. The start of a countdown is triggered by applying a brief high-level pulse to the gate. The output will pulse low for one clock period when the count reaches

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zero. The counter will remain inactive until the next hardware trigger. As for mode 1, this mode is only possible with Timer 2.

13.2.4 Read-back Commands

A timer ‘read-back’ command allows the following data to be read from a counter; the count value, status of its output signal, read/load status, configuration mode, and count mode. Two very useful ‘read-back’ tasks can be invoked by writing the bit patterns described below to the Control Register.

Task 1 - Multi Counter Latch:

A counter is latched by taking a ‘snap shot’ of the selected counter’s value and transferring that count value to the counter’s output latch register. A command to latch one or more counters can be issued by writing the bit pattern shown below to the Control Register at address 0x43:

Control Register at address 0x43.

Setting of bits CT0, CT1, and CT2 determines which counter(s) will be latched. Once latched, a program can read the count value by reading the output latch register. Addresses of latch registers are shown in Table 13-1. Two 8-bit reads of the output latch register must be carried out to read the 16-bit count value. The low byte will be obtained in the first read followed by the high byte in the second read.

Task 2 - Status of Timers:

The status information for each timer can be read via the corresponding timer data register. The command to report the status is issued by assembling the byte as shown following, and writing it to the Control Register (at address 0x43). We select the timer(s) by setting their respective control bits CT0, CT1 and CT2 of the Control Register to 1. The 8-bit status value is obtained by reading the data register of the selected timer (addresses are shown in Table 13-1). The status information is interpreted according to Figure 13-2.

Control Register at address 0x43.