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vi

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

Chapter 3

Channel Handshake

3.1

Handshake process ....................................................................................  3-2

3.2

Relationships between the channels  ..........................................................  3-6

3.3

Dependencies between channel handshake signals ..................................  3-7

Chapter 4

Addressing Options

4.1

About addressing options  ...........................................................................  4-2

4.2

Burst length  ................................................................................................  4-3

4.3

Burst size ....................................................................................................  4-4

4.4

Burst type  ...................................................................................................  4-5

4.5

Burst address  .............................................................................................  4-7

Chapter 5

Additional Control Information

5.1

Cache support  ............................................................................................  5-2

5.2

Protection unit support ................................................................................  5-5

Chapter 6

Atomic Accesses

6.1

About atomic accesses ...............................................................................  6-2

6.2

Exclusive access  ........................................................................................  6-3

6.3

Locked access ............................................................................................  6-7

Chapter 7

Response Signaling

7.1

About response signaling  ...........................................................................  7-2

7.2

Response types ..........................................................................................  7-4

Chapter 8

Ordering Model

8.1

About the ordering model  ...........................................................................  8-2

8.2

Transfer ID fields  ........................................................................................  8-3

8.3

Read ordering  .............................................................................................  8-4

8.4

Normal write ordering  .................................................................................  8-5

8.5

Write data interleaving ................................................................................  8-6

8.6

Read and write interaction ..........................................................................  8-8

8.7

Interconnect use of ID fields  .......................................................................  8-9

8.8

Recommended width of ID fields ..............................................................  8-10

Chapter 9

Data Buses

9.1

About the data buses ..................................................................................  9-2

9.2

Write strobes  ..............................................................................................  9-3

9.3

Narrow transfers  .........................................................................................  9-4

9.4

Byte invariance  ...........................................................................................  9-5

Chapter 10

Unaligned Transfers

10.1

About unaligned transfers .........................................................................  10-2

10.2

Examples ..................................................................................................  10-3

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viii

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

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ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ix

List of Tables

AMBA AXI Protocol Specification

Change history  .............................................................................................................. ii

Table 2-1

Global signals ............................................................................................................  2-2

Table 2-2

Write address channel signals  ..................................................................................  2-3

Table 2-3

Write data channel signals  ........................................................................................  2-4

Table 2-4

Write response channel signals  ................................................................................  2-5

Table 2-5

Read address channel signals  ..................................................................................  2-6

Table 2-6

Read data channel signals  ........................................................................................  2-7

Table 2-7

Low-power interface signals ......................................................................................  2-8

Table 4-1

Burst length encoding  ...............................................................................................  4-3

Table 4-2

Burst size encoding  ...................................................................................................  4-4

Table 4-3

Burst type encoding  ..................................................................................................  4-5

Table 5-1

Cache encoding  ........................................................................................................  5-3

Table 5-2

Protection encoding  ..................................................................................................  5-6

Table 6-1

Atomic access encoding  ...........................................................................................  6-2

Table 7-1

RRESP[1:0] and BRESP[1:0] encoding  ....................................................................  7-2

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Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

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