Starting a Conversion
Prescaling and
Conversion Timing
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change.
In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register. Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
Figure 91. ADC Prescaler
7-BIT ADC PRESCALER
CK
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CK/2
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CK/4
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CK/8
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CK/16
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CK/32
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CK/64
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CK/128
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ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion
195
2486O–AVR–10/04
takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 73.
Figure 92. ADC Timing Diagram, First Conversion (Single Conversion Mode)
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First Conversion |
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Next |
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Conversion |
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Cycle Number |
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25 |
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ADC Clock |
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ADEN |
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ADSC |
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ADIF |
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ADCH |
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MSB of Result |
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ADCL |
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LSB of Result |
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MUX and REFS |
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Sample & Hold |
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Conversion |
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MUX and REFS |
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Update |
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Figure 93. ADC Timing Diagram, Single Conversion |
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One Conversion |
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Next Conversion |
Cycle Number |
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ADC Clock |
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ADSC |
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ADIF |
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ADCH |
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MSB of Result |
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ADCL |
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LSB of Result |
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Sample & Hold |
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Conversion |
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MUX and REFS |
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MUX and REFS |
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Complete |
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Update |
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Update |
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196 ATmega8(L)
2486O–AVR–10/04
Changing Channel or Reference Selection
ATmega8(L)
Figure 94. ADC Timing Diagram, Free Running Conversion
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One Conversion |
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Next Conversion |
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Cycle Number |
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ADC Clock |
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ADSC |
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ADIF |
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ADCH |
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MSB of Result |
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ADCL |
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LSB of Result |
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Conversion |
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Sample &Hold |
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Table 73. ADC Conversion Time
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Sample & Hold (Cycles |
Conversion Time |
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from Start of Conversion) |
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Extended conversion |
13.5 |
25 |
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Normal conversions, single ended |
1.5 |
13 |
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The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If both ADFR and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways:
1.When ADFR or ADEN is cleared.
2.During conversion, minimum one ADC clock cycle after the trigger event.
3.After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.