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ATmega8(L)

5.This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other

devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement.

6.The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7.The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega8 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 115. Two-wire Serial Bus Timing

tof

tHIGH

SCL

tLOW

tSU;STA

tHD;STA

tHD;DAT

SDA

SU;DAT

tSU;STO

tBUF

SPI Timing

Characteristics

See Figure 116 and Figure 117 for details.

Table 102. SPI Timing Parameters

Description

Mode

Min

Typ

Max

SCK period

Master

See Table 50

SCK high/low

Master

50% duty cycle

Rise/Fall time

Master

3.6

Setup

Master

Hold

Master

Out to SCK

Master

0.5 • tSCK

SCK to out

Master

SCK to out high

Master

low to out

Slave

SCK period

Slave

4 • tck

SCK high/low(1)

Slave

2 • t

Rise/Fall time

Slave

1.6

Setup

Slave

Hold

Slave

SCK to out

Slave

SCK to

high

Slave

high to tri-state

Slave

low to SCK

Salve

2 • tck

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

-2tCLCL for fCK < 12 MHz

-3tCLCL for fCK > 12 MHz

243

2486O–AVR–10/04

Figure 116. SPI interface timing requirements (Master Mode)

SCK
(CPOL = 0)
		2	2
SCK
(CPOL = 1)
4	5		3
MISO	MSB	...	LSB
(Data Input)	MSB	...	LSB
(Data Input)
		7	8
MOSI	MSB	...	LSB
(Data Output)	MSB	...	LSB
(Data Output)

Figure 117. SPI interface timing requirements (Slave Mode)

18
SS
9			10	16
9
SCK
(CPOL = 0)
		11	11
SCK
(CPOL = 1)
13	14			12
MOSI	MSB	...	LSB
(Data Input)	MSB	...	LSB
(Data Input)
		15		17
MISO	MSB	...	LSB	X
(Data Output)	MSB	...	LSB	X
(Data Output)

244 ATmega8(L)

2486O–AVR–10/04

ATmega8(L)

ADC Characteristics

Table 103.		ADC Characteristics
Symbol		Parameter	Condition	Min(1)	Typ(1)		Max(1)		Units
		Resolution	Single Ended Conversion		10				Bits

			Single Ended Conversion
		Absolute accuracy	VREF = 4V, VCC = 4V		1.75				LSB
		(Including INL, DNL,	ADC clock = 200 kHz
		(Including INL, DNL,
		Quantization Error, Gain,	Single Ended Conversion
		and Offset Error)	Single Ended Conversion
		and Offset Error)	VREF = 4V, VCC = 4V		3				LSB
			VREF = 4V, VCC = 4V		3				LSB
			ADC clock = 1 MHz

			Single Ended Conversion
			VREF = 4V, VCC = 4V
		Integral Non-linearity (INL)	ADC clock = 200 kHz		0.75				LSB

			Single Ended Conversion
		Differential Non-linearity	VREF = 4V, VCC = 4V
		(DNL)	ADC clock = 200 kHz		0.5				LSB

		Gain Error	Single Ended Conversion		1				LSB
			VREF = 4V, VCC = 4V
			ADC clock = 200 kHz

		Offset Error	Single Ended Conversion		1				LSB
			VREF = 4V, VCC = 4V
			ADC clock = 200 kHz

		Conversion Time	Free Running Conversion	13				260	µs

		Clock Frequency		50			1000		kHz

AV	CC	Analog Supply Voltage		V - 0.3(2)		V	CC	+ 0.3(3)	V
	CC			CC			CC
VREF		Reference Voltage		2.0			AVCC		V
VIN		Input voltage		GND			VREF		V
		Input bandwidth			38.5				kHz

VINT		Internal Voltage Reference		2.3	2.56			2.7	V
RREF		Reference Input Resistance			32				kΩ
RAIN		Analog Input Resistance		55	100				MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V.

245

2486O–AVR–10/04

ATmega8 Typical

Characteristics

Active Supply Current

The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail- to-Rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Figure 118. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY