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I/O Memory

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

The I/O space definition of the ATmega8 is shown in “” on page 284.

All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

22 ATmega8(L)

2486O–AVR–10/04

ATmega8(L)

System Clock and

Clock Options

Clock Systems and their Distribution

Figure 10 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 31. The clock systems are detailed Figure 10.

Figure 10. Clock Distribution

Asynchronous		General I/O
Timer/Counter		Modules

clkI/O

clkASY





Timer/Counter			External RC
Oscillator			Oscillator

ADC	CPU Core	RAM	Flash and
ADC	CPU Core	RAM	EEPROM
			EEPROM
clkADC
AVR Clock	clkCPU
Control Unit
	clkFLASH
	Reset Logic	Watchdog Timer
Source Clock	Watchdog Clock
Clock		Watchdog
Multiplexer		Oscillator
	Crystal	Low-Frequency	Calibrated RC
External Clock	Oscillator	Crystal Oscillator	Oscillator

CPU Clock – clkCPU	The CPU clock is routed to parts of the system concerned with operation of the AVR
	core. Examples of such modules are the General Purpose Register File, the Status Reg-
	ister and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the
	core from performing general operations and calculations.
I/O Clock – clkI/O	The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
	USART. The I/O clock is also used by the External Interrupt module, but note that some
	external interrupts are detected by asynchronous logic, allowing such interrupts to be
	detected even if the I/O clock is halted. Also note that address recognition in the TWI
	module is carried out asynchronously when clkI/O is halted, enabling TWI address recep-
	tion in all sleep modes.
Flash Clock – clkFLASH	The Flash clock controls operation of the Flash interface. The Flash clock is usually
	active simultaneously with the CPU clock.

2486O–AVR–10/04

Asynchronous Timer Clock – The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked

clkASY	directly from an external 32 kHz clock crystal. The dedicated clock domain allows using
	this Timer/Counter as a real-time counter even when the device is in sleep mode. The
	Asynchronous Timer/Counter uses the same XTAL pins as the CPU main clock but
	requires a CPU main clock frequency of more than four times the Oscillator frequency.
	Thus, asynchronous operation is only available while the chip is clocked on the Internal
	Oscillator.
ADC Clock – clkADC	The ADC is provided with a dedicated clock domain. This allows halting the CPU and
	I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-
	rate ADC conversion results.

Clock Sources

The device has the following clock source options, selectable by Flash Fuse Bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 2. Device Clocking Options Select(1)

Device Clocking Option	CKSEL3..0

External Crystal/Ceramic Resonator	1111 - 1010

External Low-frequency Crystal	1001

External RC Oscillator	1000 - 0101

Calibrated Internal RC Oscillator	0100 - 0001

External Clock	0000

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega8 Typical Characteristics”. The device is shipped with CKSEL = “0001” and SUT = “10” (1 MHz Internal RC Oscillator, slowly rising power).

Table 3. Number of Watchdog Oscillator Cycles