Файл: Beginers introduction to the Assebly Language of ATMEL-AVR Microprocessors (Gerhard Schmidt,2003, англ).pdf

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Avr-Asm-Tutorial

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http://www.avr-asm-tutorial.net

Function

Conditioned

Jump

Conditioned

Jumps

Others

Subfunction

Command

Flags

Clk

Statusbit set

BRBS b7,c127

1/2

Statusbit clear

BRBC b7,c127

1/2

Jump if equal

BREQ c127

1/2

Jump if equal

BRNE c127

1/2

Jump if carry

BRCS c127

1/2

Jump if carry clear

BRCC c127

1/2

Jump if equal or greater

BRSH c127

1/2

Jump if lower

BRLO c127

1/2

Jump if negative

BRMI c127

1/2

Jump if positive

BRPL c127

1/2

Jump if greater or equal (Signed)

BRGE c127

1/2

Jump if lower than zero (Signed)

BRLT c127

1/2

Jump on half carry set

BRHS c127

1/2

Jump if half carry clear

BRHC c127

1/2

Jump if T-Flag set

BRTS c127

1/2

Jump if T-Flag clear

BRTC c127

1/2

Jump if Twos complement carry set

BRVS c127

1/2

Jump if Twos complement carry clear

BRVC c127

1/2

Jump if Interrupts enabled

BRIE c127

1/2

Jump if Interrupts disabled

BRID c127

1/2

Registerbit=0

SBRC r1,b7

1/2/3

Registerbit=1

SBRS r1,b7

1/2/3

Portbit=0

SBIC pl,b7

1/2/3

Portbit=1

SBIS pl,b7

1/2/3

Compare, jump if equal

CPSE r1,r2

1/2/3

No Operation

NOP

1

Sleep

SLEEP

1

Watchdog Reset

WDR

1

Command list in alphabetic order

Assembler directives

.CSEG

.DB

.DEF

.DW

.ENDMACRO

.ESEG

.EQU

.INCLUDE

.MACRO

.ORG

Commands

ADC r1,r2

ADD r1,r2

ADIW rd,k63

AND r1,r2

ANDI rh,c255, Register

ASR r1

BLD r1,b7

BRCC c127

BRCS c127

BREQ c127

BRGE c127

BRHC c127

BRHS c127

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BRID c127

BRIE c127

BRLO c127

BRLT c127

BRMI c127

BRNE c127

BRPL c127

BRSH c127

BRTC c127

BRTS c127

BRVC c127

BRVS c127

BST r1,b7

CBI pl,b7

CBR rh,255, Register

CLC

CLH

CLI

CLN

CLR r1

CLS

CLT, (command example)

CLV

CLZ

COM r1

CP r1,r2

CPC r1,r2

CPI rh,c255, Register

CPSE r1,r2

DEC r1

EOR r1,r2

ICALL

IJMP IN r1,p1

INC r1

LD rp,(rp,rp+,-rp) (Register), (SRAM access), Ports

LDD r1,ry+k63

LDI rh,c255 (Register), Pointer

LDS r1,c65535

LPM

LSL r1

LSR r1

MOV r1,r2

NEG r1

NOP

OR r1,r2 ORI rh,c255 OUT p1,r1

POP r1, (in Int-routine)

PUSH r1, (in Int-routine)

RCALL c4096

RET, (in Int-routine)

RETI

RJMP c4096

ROL r1

ROR r1

SBC r1,r2

SBCI rh,c255

SBI pl,b7

SBIC pl,b7

SBIS pl,b7

SBIW rd,k63

SBR rh,255, Register

SBRC r1,b7

SBRS r1,b7

SEC

SEH

SEI, (in Int-routine)

SEN

SER rh

SES

SET, (example)

SEV

SEZ

SLEEP

ST (rp/rp+/-rp),r1 (Register), SRAM access, Ports

STD ry+k63,r1

STS c65535,r1

SUB r1,r2

SUBI rh,c255

SWAP r1

TST r1

WDR

Avr-Asm-Tutorial

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Port details

The table of the relevant ports in the ATMEL AVR types AT90S2313, 2323 and 8515. Bytewise accessable ports or register pairs are not displayed in detail. No warranty for correctness, see the original data sheets!

Status­Register, Accumulator flags

Port

Function

Port-Address

RAM-Address

SREG

Status Register Accumulator

0x3F

0x5F

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

Bit

Name

Meaning

Opportunities

Conmmand

7

I

Global Interrupt Flag

0: Interrupts disabled

CLI

1: Interrupts enabled

SEI

6

T

Bit storage

0: Stored bit is 0

CLT

1: Stored bit is 1

SET

5

H

Halfcarry-Flag

0: No halfcarry occured

CLH

1: Halfcarry occured

SEH

4

S

Sign-Flag

0: Sign positive

CLS

1: Sign negative

SES

3

V

Two's complement-Flag

0: No carry occured

CLV

1: Carry occured

SEV

2

N

Negative-Flag

0: Result was not negative/smaller

CLN

1: Result was negative/smaller

SEN

1

Z

Zero-Flag

0: Result was not zero/unequal

CLZ

1: Result was zero/equal

SEZ

0

C

Carry-Flag

0: No carry occured

CLC

1: Carry occured

SEC

Stackpointer

Port

Function

Port-Address

RAM-Address

SPL/SPH

Stackpointer

003D/0x3E

0x5D/0x5E

Name

Meaning

Availability

SPL

Low-Byte of

From AT90S2313 upwards, not in 1200

Stackpointer

SPH

High-Byte of

From AT90S8515 upwards, only in devices with >256 bytes internal SRAM

Stackpointer

SRAM and External Interrupt control

Port

Function

Port-Address

RAM-Address

MCUCR

MCU General Control Register

0x35

0x55

7

6

5

4

3

2

1

0

SRE

SRW

SE

SM

ISC11

ISC10

ISC01

ISC00

Bit

Name

Meaning

Opportunities

7

SRE

Ext.SRAM Enable

0=No external SRAM connected

1=External SRAM connected

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Bit

Name

Meaning

Opportunities

6

SRW

Ext.SRAM Wait States

0=No extra wait state on external SRAM

1=Additional wait state on external SRAM

5

SE

Sleep Enable

0=Ignore SLEEP commands

1=SLEEP on command

4

SM

Sleep Mode

0=Idle Mode (Half sleep)

1=Power Down Mode (Full sleep)

3

ISC11

00: Low-level initiates Interrupt

Interrupt control Pin INT1

01: Undefined

(connected to GIMSK)

2

ISC10

10: Falling edge triggers interrupt

11: Rising edge triggers interrupt

1

ISC01

00: Low-level initiates interrupt

Interrupt control Pin INT0

01: Undefined

(connected to GIMSK)

0

ISC00

10: Falling edge triggers interrupt

11: Rising edge triggers interrupt

External Interrupt Control

Port

Function

Port-Address

RAM-Address

GIMSK

General Interrupt Maskregister

0x3B

0x5B

7

6

5

4

3

2

1

0

INT1

INT0

-

-

-

-

-

-

Bit

Name

Meaning

Opportunities

7

INT1

Interrupt by external pin INT1

0: External INT1 disabled

(connected to mode in MCUCR)

1: External INT1 enabled

6

INT0

Interrupt by external Pin INT0

0: External INT0 disabled

(connected to mode in MCUCR)

1: External INT0 enabled

0...5

(Not used)

Port

Function

Port-Address

RAM-Address

GIFR

General Interrupt Flag Register

0x3A

0x5A

7

6

5

4

3

2

1

0

INTF1

INTF0

-

-

-

-

-

-

Bit

Name

Meaning

Opportunities

7

INTF1

Interrupt by external pin INT1 occured

Automatic clear by execution of the Int-Routine or

Clear by command

6

INTF0

Interrupt by external pin INT0 occured

0...5

(Not used)

Timer Interrupt Control

Port

Function

Port-Address

RAM-Address

TIMSK

Timer Interrupt Maskregister

0x39

0x59

7

6

5

4

3

2

1

0

TOIE1

OCIE1A

OCIE1B

-

TICIE1

-

TOIE0

-

Avr-Asm-Tutorial

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Bit

Name

Meaning

Opportunities

7

TOIE1

Timer/Counter 1 Overflow-Interrupt

0: No Int at overflow

1: Int at overflow

6

OCIE1A

Timer/Counter 1 Compare A Interrupt

0: No Int at equal A

1: Int at equal A

5

OCIE1B

Timer/Counter 1 Compare B Interrupt

0: No Int at B

1: Int at equal B

4

(Not used)

3

TICIE1

Timer/Counter 1 Capture Interrupt

0: No Int at Capture

1: Int at Capture

2

(Not used)

1

TOIE0

Timer/Counter 0 Overflow-Interrupt

0: No Int at overflow

1: Int at overflow

0

(Not used)

Port

Function

Port-Address

RAM-Address

TIFR

Timer Interrupt Flag Register

0x38

0x58

7

6

5

4

3

2

1

0

TOV1

OCF1A

OCF1B

-

ICF1

-

TOV0

-

Bit

Name

Meaning

Opportunities

7

TOV1

Timer/Counter 1 Overflow reached

Interrupt-Mode:

6

OCF1A

Timer/Counter 1 Compare A reached

Automatic Clear

by execution of the

5

OCF1B

Timer/Counter 1 Compare B reached

Int-Routine

4

(Not used)

OR

3

ICF1

Timer/Counter 1 Capture-Event occured

2

(not used)

Polling-Mode:

1

TOV0

Timer/Counter 0 Overflow occured

Clear by

command

0

(not used)

Timer/Counter 0

Port

Function

Port-Address

RAM-Address

TCCR0

Timer/Counter 0 Control Register

0x33

0x53

7

6

5

4

3

2

1

0

-

-

-

-

-

CS02

CS01

CS00

Bit

Name

Meaning

Opportunities

000: Stop Timer

001: Clock = Chip clock

010: Clock = Chip clock / 8

2.. 0

CS02..CS00

Timer Clock

011: Clock = Chip clock / 64

100: Clock = Chip clock / 256

101: Clock = Chip clock / 1024

110: Clock = falling edge of external Pin T0

111: Clock = rising edge of external Pin T0

3..7

(not used)

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