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13.4 Sequential Memory: FIFO and LIFO

K E Y T E R M S

Sequential memory Memory in which the stored data cannot be read or written in random order, but must be addressed in a specific sequence.

FIFO First-in first-out. A sequential memory in which the stored data can be read only in the order in which it was written.

Queue A FIFO memory.

LIFO Last-in first-out. A sequential memory in which the last data written are the first data read.

Stack A LIFO memory.

The RAM and ROM devices we have examined up until now have all been random access devices. That is, any data could be read from or written to any sequence of addresses in any order. There is another class of memory in which the data must be accessed in a particular order. Such devices are called sequential memory.

There are two main ways of organizing a sequential memory—as a queue or as a stack. Figure 13.21 shows the arrangement of data in each of these types of memory.

A queue is a first-in first-out (FIFO) memory, meaning that the data can be read only in the same order they are written, much as railway cars always come out of a tunnel in the same order they go in.

One common use for FIFO memory is to connect two devices that have different data rates. For instance, a computer can send data to a printer much faster than the printer can use it. To keep the computer from either waiting for the printer to print everything or periodically interrupting the computer’s operation to continue the print task, data can be sent in a burst to a FIFO, where the printer can read them as needed. The only proviso is that there

FIGURE 13.21

Sequential Memory

646 C H A P T E R 1 3 • Memory Devices and Systems

must be some logic signal to the computer telling it when the queue is full and not to send more data and another signal to the printer letting it know that there are some data to read from the queue.

The last-in-first-out (LIFO), or stack, memory configuration, also shown in Figure 13.21, is not available as a special chip, but rather is a way of organizing RAM in a memory system.

The term “stack” is analogous to the idea of a spring-loaded stack of plates in a cafeteria line. When you put a bunch of plates on the stack, they settle into the recessed storage area. When a plate is removed, the stack springs back slightly and brings the second plate to the top level. (The other plates, of course, all move up a notch.) The top plate is the only one available for removal from the stack, and plates are always removed in reverse order from that in which they were loaded.

Figure 13.21b shows how data are transferred to and from a LIFO memory. A block of addresses in a RAM is designated as a stack, and one or two bytes of data in the RAM store a number called the stack pointer, which is the current address of the top of the stack.

In Figure 13.21, the value of the stack pointer changes with every change of data in the stack, pointing to the last-in data in every case. When data are removed from the stack, the stack pointer is used to locate the data that must be read first. After the read, the stack pointer is modified to point to the next-out data. Some stack configurations have the stack pointer painting to the next empty location on the stack.

The most common application for LIFO memory is in a computer system. If a program is interrupted during its execution by a demand from the program or some piece of hardware that needs attention, the status of various registers within the computer are stored on a stack and the computer can pay attention to the new demand, which will certainly change its operating state. After the interrupting task is finished, the original operating state of the computer can be taken from the top of the stack and reloaded into the appropriate registers, and the program can resume where it left off.

SECTION 13.4 REVIEW PROBLEM

13.4 State the main difference between a stack and a queue.

13.5Dynamic RAM Modules

K E Y T E R M S

Memory module A small circuit board containing several dynamic RAM chips.

Dynamic RAM chips are often combined on a small circuit board to make a memory module. This is because the data bus widths of systems requiring the DRAMs are not always the same as the DRAMs themselves. For example, Figure 13.22 shows how four 64M8 DRAMs are combined to make a 64M 32 memory module. The block diagram of the module is shown in Figure 13.22, and the mechanical outline is shown in Figure 13.23. The data input/output lines are separate from one another so that there are 32 data I/Os (DQ). The address lines (ADDR[12..0]) for the module are parallel on all chips. With address multiplexing, this 13-bit address bus yields a 26-bit address, giving a 64M address range. Chip selects (CS) for all devices are connected together so that selecting the module selects all chips on the module.

This particular memory module is configured as a single in-line memory module (SIMM), which has the DRAM chips and pin connections on one side of the board only. A

RAS

CAS

CS

64M 8

DQ[8..15]

RAS

CAS

CS

64M 8

DQ[16..23]

RAS

CAS

CS

64M 8

DQ[24..32]

RAS

CAS

CS

FIGURE 13.23

SIMM Layout

dual in-line memory module (DIMM) has the DRAMs mounted on both sides of the circuit board and pin connections on both sides of the board as well.

SECTION 13.5 REVIEW PROBLEM

13.5A SIMM has a capacity of 16M 32. How many 16M 8 DRAMs are required to make this SIMM? How many address lines does the SIMM require? How should the DRAMs be connected?

648C H A P T E R 1 3 • Memory Devices and Systems

13.6Memory Systems

K E Y T E R M S

Address decoder A circuit enabling a particular memory device to be selected by the address bus of a larger memory system.

Address space A block of addresses in a memory system.

Bus contention The condition that results when two or more devices try to send data to a bus at the same time. Bus contention can damage the output buffers of the devices involved.

Memory map A diagram showing the total address space of a memory system and the placement of various memory devices within that space.

In the section on memory modules, we saw how multiple memory devices can be combined to make a system that has the same number of addressable locations as the individual devices making up the system, but with a wider data bus. We can also create memory systems where the data I/O width of the system is the same as the individual chips, but where the system has more addressable locations than any chip within the system.

In such a system, the data I/O and control lines from the individual memory chips

Figure 13.25 shows a memory map of the 64K 8 SRAM system, indicating the range of addresses for each device in the system. The total range of addresses in the system is called the address space.

WE

CS

a. Single 32 K 8 SRAM

32 K 8 SRAM

A[14..0]

32 K 8 SRAM

A[14..0]

DQ[7 ..0]

WE

CS1

b. Two 32 K 8 SRAMS connected to make 64 K 8 SRAM system

FIGURE 13.24

Expanding Memory Space

FIGURE 13.25 0000H

Memory Map

SRAM0

8000H

SRAM1

FFFFH