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Circuit Design
with VHDL
Volnei A. Pedroni
TLFeBOOK
Circuit Design with VHDL
TLFeBOOK
TLFeBOOK
Circuit Design with VHDL
Volnei A. Pedroni
MIT Press
Cambridge, Massachusetts
London, England
TLFeBOOK
6 2004 Massachusetts Institute of Technology
All rights reserved. No part of this book may be reproduced in any form by any electronic or mechanical means (including photocopying, recording, or information storage and retrieval) without permission in writing from the publisher.
This book was set in Times New Roman on 3B2 by Asco Typesetters, Hong Kong and was printed and bound in the United States of America.
Library of Congress Cataloging-in-Publication Data
Pedroni, Volnei A.
Circuit design with VHDL/Volnei A. Pedroni. p. cm.
Includes bibliographical references and index. ISBN 0-262-16224-5 (alk. paper)
1. |
VHDL (Computer hardware description language) 2. Electronic circuit design. |
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3. |
System design. I. Title. |
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TK7885.7.P43 |
2004 |
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621.3905—dc22 |
2004040174 |
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10 |
9 8 7 6 5 |
4 3 2 1 |
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TLFeBOOK
To Claudia, Patricia, Bruno, and Ricardo
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Contents
Preface |
xi |
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I |
CIRCUIT DESIGN |
1 |
|
1 |
Introduction |
3 |
|
1.1 |
About VHDL |
3 |
|
1.2 |
Design Flow |
3 |
|
1.3 |
EDA Tools |
4 |
|
1.4 |
Translation of VHDL Code into a Circuit |
5 |
|
1.5 |
Design Examples |
8 |
|
2 |
Code Structure |
13 |
|
2.1 |
Fundamental VHDL Units |
13 |
|
2.2 |
LIBRARY Declarations |
13 |
|
2.3 |
ENTITY |
15 |
|
2.4 |
ARCHITECTURE |
17 |
|
2.5 |
Introductory Examples |
17 |
|
2.6 |
Problems |
22 |
|
3 |
Data Types |
25 |
|
3.1 |
Pre-Defined Data Types |
25 |
|
3.2 |
User-Defined Data Types |
28 |
|
3.3 |
Subtypes |
29 |
|
3.4 |
Arrays |
30 |
|
3.5 |
Port Array |
33 |
|
3.6 |
Records |
35 |
|
3.7 |
Signed and Unsigned Data Types |
35 |
|
3.8 |
Data Conversion |
37 |
|
3.9 |
Summary |
38 |
|
3.10 |
Additional Examples |
38 |
|
3.11 |
Problems |
43 |
|
4 |
Operators and Attributes |
47 |
|
4.1 |
Operators |
47 |
|
4.2 |
Attributes |
50 |
|
4.3 |
User-Defined Attributes |
52 |
|
4.4 |
Operator Overloading |
53 |
|
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viii |
Contents |
4.5 |
GENERIC |
54 |
|
4.6 |
Examples |
55 |
|
4.7 |
Summary |
60 |
|
4.8 |
Problems |
61 |
|
5 |
Concurrent Code |
65 |
|
5.1 |
Concurrent versus Sequential |
65 |
|
5.2 |
Using Operators |
67 |
|
5.3 |
WHEN (Simple and Selected) |
69 |
|
5.4 |
GENERATE |
78 |
|
5.5 |
BLOCK |
81 |
|
5.6 |
Problems |
84 |
|
6 |
Sequential Code |
91 |
|
6.1 |
PROCESS |
91 |
|
6.2 |
Signals and Variables |
93 |
|
6.3 |
IF |
94 |
|
6.4 |
WAIT |
97 |
|
6.5 |
CASE |
100 |
|
6.6 |
LOOP |
105 |
|
6.7 |
CASE versus IF |
112 |
|
6.8 |
CASE versus WHEN |
113 |
|
6.9 |
Bad Clocking |
114 |
|
6.10 |
Using Sequential Code to Design Combinational Circuits |
118 |
|
6.11 |
Problems |
121 |
|
7 |
Signals and Variables |
129 |
|
7.1 |
CONSTANT |
129 |
|
7.2 |
SIGNAL |
130 |
|
7.3 |
VARIABLE |
131 |
|
7.4 |
SIGNAL versus VARIABLE |
133 |
|
7.5 |
Number of Registers |
140 |
|
7.6 |
Problems |
151 |
|
8 |
State Machines |
159 |
|
8.1 |
Introduction |
159 |
|
8.2 |
Design Style #1 |
160 |
|
8.3 |
Design Style #2 (Stored Output) |
168 |
|
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Contents |
ix |
8.4 |
Encoding Style: From Binary to OneHot |
181 |
|
8.5 |
Problems |
183 |
|
9 |
Additional Circuit Designs |
187 |
|
9.1 |
Barrel Shifter |
187 |
|
9.2 |
Signed and Unsigned Comparators |
191 |
|
9.3 |
Carry Ripple and Carry Look Ahead Adders |
194 |
|
9.4 |
Fixed-Point Division |
198 |
|
9.5 |
Vending-Machine Controller |
202 |
|
9.6 |
Serial Data Receiver |
208 |
|
9.7 |
Parallel-to-Serial Converter |
211 |
|
9.8 |
Playing with a Seven-Segment Display |
212 |
|
9.9 |
Signal Generators |
217 |
|
9.10 |
Memory Design |
220 |
|
9.11 |
Problems |
225 |
|
II |
SYSTEM DESIGN |
231 |
|
10 |
Packages and Components |
233 |
|
10.1 |
Introduction |
233 |
|
10.2 |
PACKAGE |
234 |
|
10.3 |
COMPONENT |
236 |
|
10.4 |
PORT MAP |
244 |
|
10.5 |
GENERIC MAP |
244 |
|
10.6 |
Problems |
251 |
|
11 |
Functions and Procedures |
253 |
|
11.1 |
FUNCTION |
253 |
|
11.2 |
Function Location |
256 |
|
11.3 |
PROCEDURE |
265 |
|
11.4 |
Procedure Location |
266 |
|
11.5 |
FUNCTION versus PROCEDURE Summary |
270 |
|
11.6 |
ASSERT |
270 |
|
11.7 |
Problems |
271 |
|
12 |
Additional System Designs |
275 |
|
12.1 |
Serial-Parallel Multiplier |
275 |
|
12.2 |
Parallel Multiplier |
279 |
|
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x |
Contents |
12.3 |
Multiply-Accumulate Circuits |
285 |
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12.4 |
Digital Filters |
289 |
|
12.5 |
Neural Networks |
294 |
|
12.6 |
Problems |
301 |
|
Appendix A: Programmable Logic Devices |
305 |
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Appendix B: |
Xilinx ISE BModelSim Tutorial |
317 |
|
Appendix C: |
Altera MaxPlus II BAdvanced Synthesis Software |
||
Tutorial |
329 |
||
Appendix D: Altera Quartus II Tutorial |
343 |
||
Appendix E: VHDL Reserved Words |
355 |
||
Bibliography |
357 |
||
Index |
359 |
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TLFeBOOK
Preface
Structure of the Book
The book is divided into two parts: Circuit Design and System Design. The first part deals with everything that goes directly inside the main code, while the second deals with units that might be located in a library (for code sharing, reuse, and partitioning).
In summary, in Part I we study the entire background and coding techniques of VHDL, which includes the following:
Code structure: libraries, entity, architecture (chapter 2)
Data types (chapter 3)
Operators and attributes (chapter 4)
Concurrent statements and concurrent code (chapter 5)
Sequential statements and sequential code (chapter 6)
Objects: signals, variables, constants (chapter 7)
Design of finite state machines (chapter 8)
And, finally, additional circuit designs are presented (chapter 9).
Then, in Part II we simply add new building blocks, which are intended mainly for library allocation, to the material already presented. The structure of Part II is the following:
Packages and components (chapter 10)
Functions and procedures (chapter 11)
Finally, additional system designs are presented (chapter 12).
Distinguishing Features
The main distinguishing features of the book are the following:
It teaches in detail all indispensable features of VHDL synthesis in a concise format.
The sequence is well established. For example, a clear distinction is made between what is at the circuit level (Part I) versus what is at the system level (Part II). The foundations of VHDL are studied in chapters 1 to 4, fundamental coding in chapters 5 to 9, and finally system coding in chapters 10 to 12.
Each chapter is organized in such a way to collect together related information as closely as possible. For instance, concurrent code is treated collectively in one chap-
TLFeBOOK
xii |
Preface |
ter, while sequential code is treated in another; data types are discussed in one chapter, while operators and attributes are in another; what is at the circuit level is seen in one part of the book, while what is at the system level is in another.
While books on VHDL give limited emphasis to digital design concepts, and books on digital design discuss VHDL only briefly, the present work completely integrates them. It is indeed a design-oriented approach.
To achieve the above-mentioned integration between VHDL and digital design, the following steps are taken:
a large number of complete design examples (rather than sketchy or partial solutions) are presented;
illustrative top-level circuit diagrams are always shown;
fundamental design concepts are reviewed;
the solutions are explained and commented;
the circuits are always physically implemented (using programmable logic devices);
simulation results are always included, along with analysis and comments;
finally, appendices on programmable devices and synthesis tools are also included.
Audience
The book is intended as a text for any of the following EE/CS courses:
VHDL
Automated Digital Design
Programmable Logic Devices
Digital Design (basic or advanced)
It is also a supporting text for in-house courses in any of the areas listed above, particularly for vendor-provided courses on VHDL and/or programmable logic devices.
Acknowledgments
To the anonymous reviewers for their invaluable comments and suggestions. Special thanks also to Ricardo P. Jasinski and Bruno U. Pedroni for their reviews and comments.
TLFeBOOK