Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

FIGURE 9.13

Example 9.4

Complete State Diagram

SECTION 9.2 REVIEW PROBLEM

9.2A 4-bit synchronous counter based on JK flip-flops is described by the following set of equations:

376 C H A P T E R 9 • Counters and Shift Registers

Assume the counter output is at 1000 in the count sequence. What will the output be after one clock pulse? After two clock pulses?

9.3 Design of Synchronous Counters

K E Y T E R M S

Excitation table A table showing the required input conditions for every possible transition of a flip-flop output.

State machine A synchronous sequential circuit.

A synchronous counter can be designed using established techniques that involve the derivation of Boolean equations for the counter’s next state logic. Alternatively, several VHDL structures can be used to define counters; we can use a behavioral description of the counter, or we can use a state machine definition in VHDL that specifies each present and next state explicitly.

In addition to the classical counter design techniques, we will examine the design of a counter through a behavioral description in VHDL. We will leave the state machine design for the following chapter.

Classical Design Technique

There are several steps involved in the classical design of a synchronous counter.

1.Define the problem. Before you can begin design of a circuit, you have to know what its purpose is and what it should do under all possible conditions.

2.Draw a state diagram showing the progression of states under various input conditions and what outputs the circuit should produce, if any.

3.Make a state table which lists all possible Present States and the Next State for each one. List the present states in binary order.

4.Use flip-flop excitation tables to determine at what states the flip-flop synchronous inputs must be to make the circuit go from each Present State to its Next State.

5.The logic levels of the synchronous inputs are Boolean functions of the flip-flop outputs and the control inputs. Simplify the expression for each input and write the simplified Boolean expression.

6.Use the Boolean expressions found in step 5 to draw the required logic circuit.

Flip-flop Excitation Tables

In the synchronous counter circuits we examined earlier in this chapter, we used JK flipflops that were configured to operate only in toggle or no change mode. We can use any type of flip-flop for a synchronous sequential circuit. If we choose to use JK flip-flops, we can use any of the modes (no change, reset, set, or toggle) to make transitions from one state to another.

A flip-flop excitation table shows all possible transitions of a flip-flop output and the synchronous input levels needed to effect these transitions. Table 9.7 is the excitation table of a JK flip-flop.

If we want a flip-flop to make a transition from 0 to 1, we can use either the toggle function (JK 11) or the set function (JK 10). It doesn’t matter what K is, as long as J 1. This is reflected by the variable pair (JK 1X) beside the 0→ 1 entry in Table 9.7. The X is a don’t care state, a 0 or 1 depending on which is more convenient for the simplification of the Boolean function of the J or K input affected.

Table 9.8 shows a condensed version of the JK flip-flop excitation table.

378 C H A P T E R 9 • Counters and Shift Registers

Table 9.9 State Table for a Mod-12 Counter

Let us examine one transition to show how the table is completed. The transition from Q3Q2Q1Q0 0101 to Q3Q2Q1Q0 0110 consists of the following individual flipflop transitions.

The other lines of the table are similarly completed.

5.Simplify the Boolean expression for each input. Table 9.9 can be treated as eight truth tables, one for each J or K input. We can simplify each function by Boolean algebra or by using a Karnaugh map.

Figure 9.15 shows K-map simplification for all 8 synchronous inputs. These maps yield the following simplified Boolean expressions.

J0 1

K0 1

J1 Q0

K1 Q0

J2 Q3Q1Q0

K2 Q1Q0

J3 Q2Q1Q0

K3 Q1Q0

6.Draw the required logic circuit. Figure 9.16 shows the circuit corresponding to the above Boolean expressions.

We have assumed that states 1100 to 1111 will never occur in the operation of the mod-12 counter. This is normally the case, but when the circuit is powered up, there is no guarantee that the flip-flops will be in any particular state.

If a counter powers up in an unused state, the circuit should enter the main sequence after one or more clock pulses. To test whether or not this happens, let us make a state