11.7 • Internal Circuitry of TTL Gates |
537 |
FIGURE 11.41
Tristate Inverters
Table 11.6 Truth Tables of Tristate
Inverters
G |
A |
Y |
|
A |
Y |
G |
|
|
|
|
|
|
0 |
0 |
Hi-Z |
0 |
0 |
1 |
0 |
1 |
Hi-Z |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
Hi-Z |
1 |
1 |
0 |
1 |
1 |
Hi-Z |
|
|
|
|
|
|
538 C H A P T E R 1 1 • Logic Gate Circuitry
SECTION 11.7D REVIEW PROBLEM
11.10Why is the diode from the base of Q4 necessary in the tristate inverters in Figure 11.41?
Other Basic TTL Gates
Other TTL gates are similar to the NAND and inverter gates we have already examined. A significant variation is the OR/NOR circuit, which has a different input configuration than the AND/NAND/inverter type gates.
7402 NOR Gate
Figure 11.42 shows one gate of a 7402 quadruple 2-input NOR gate package. The difference between this gate and the 7400 NAND gate is the structure of the inputs. The NOR gate does not use the multiple-emitter transistor, but rather an individual transistor (Q1 or Q2) for each input. There are two phase splitters (Q3 and Q4), which are paralleled, emitter- to-emitter and collector-to-collector.
FIGURE 11.42
7402 NOR Gate Circuit
If either Q3 or Q4 is enabled by a HIGH at its corresponding input, it will turn on Q5, making the output LOW.
If both gate inputs are LOW, both Q3 and Q4 are in cutoff mode, and so is Q5. The output is HIGH through Q6.
Table 11.7 shows the truth table and the states of the transistors for this gate. It is not strictly correct to refer to Q1 and Q2 as being ON or OFF, since there is current flowing in these transistors regardless of whether the inputs are HIGH or LOW. Let us define the ON
|
|
|
11.8 • |
Internal Circuitry of MOS Gates |
539 |
Table 11.7 7402 NOR Function and Truth Table |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A B |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Y |
|
|
|
|
|
|
|
|
|
|
|
|
0 |
0 |
ON |
ON |
OFF |
OFF |
OFF |
ON |
1 |
|
|
0 |
1 |
ON |
OFF |
OFF |
ON |
ON |
OFF |
0 |
|
|
1 |
0 |
OFF |
ON |
ON |
OFF |
ON |
OFF |
0 |
|
|
1 |
1 |
OFF |
OFF |
ON |
ON |
ON |
OFF |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
state of an input transistor as the condition where the base-emitter junction is conducting (LOW input). If the base-collector junction conducts, we will consider the transistor OFF (HIGH input).
7408 AND Gate and 7432 OR Gate
It may not be obvious why we would choose to study NAND and NOR gates before AND and OR. After all, AND and OR are the more basic logic functions.
Electrically, it works the other way around. The simplest TTL circuit is the NAND/inverter, followed by the NOR. AND and OR gates are more complex since they are based on the NAND and NOR and require an extra inverter stage.
FIGURE 11.43
7408 AND Gate
Figure 11.43 shows the circuit of a 7408 AND gate, and Figure 11.44 shows a 7432 TTL OR gate circuit. Each of these gates is like its NAND/NOR counterpart, except for an additional inverter, implemented by Q3 in the AND gate and Q5 in the OR gate.
Tables 11.8 and 11.9 show the transistor function and truth table for each gate. In keeping with the convention established for the NOR function table, an input transistor with a conducting base-emitter junction is considered ON.
540 C H A P T E R 1 1 • Logic Gate Circuitry
FIGURE 11.44
7432 OR Gate
|
|
Table 11.8 7408 AND Function and Truth Table |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A B |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0 |
0 |
ON |
OFF |
OFF |
ON |
ON |
OFF |
0 |
|
|
|
0 |
1 |
ON |
OFF |
OFF |
ON |
ON |
OFF |
0 |
|
|
|
1 |
0 |
ON |
OFF |
OFF |
ON |
ON |
OFF |
0 |
|
|
|
1 |
1 |
OFF |
ON |
ON |
OFF |
OFF |
ON |
1 |
|
|
|
|
|
|
|
|
|
|
Table 11.9 7432 OR Function and Truth Table |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A B |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
Q8 |
Y |
|
|
|
|
|
|
|
|
|
|
|
|
|
0 |
0 |
|
ON |
ON |
OFF |
OFF |
OFF |
ON |
ON |
OFF |
0 |
0 |
1 |
|
ON |
OFF |
OFF |
ON |
ON |
OFF |
OFF |
ON |
1 |
1 |
0 |
|
OFF |
ON |
ON |
OFF |
ON |
OFF |
OFF |
ON |
1 |
1 |
1 |
|
OFF |
OFF |
ON |
ON |
ON |
OFF |
OFF |
ON |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
SECTION 11.7E REVIEW PROBLEM
11.11 Why are noninverting gates more complex than inverting gates?
11.8Internal Circuitry of MOS Gates
K E Y T E R M S
MOSFET Metal-oxide-semiconductor field effect transistor. A MOSFET has three terminals—gate, source, and drain—which are analogous to the base, emitter, and collector of a bipolar junction transistor.
11.8 • Internal Circuitry of MOS Gates |
541 |
Enhancement-mode MOSFET A MOSFET that creates a conduction path (a channel) between its drain and source terminals when the voltage between gate and source exceeds a specified threshold level.
Substrate The foundation of n- or p-type silicon on which an integrated circuit is built.
n-channel enhancement-mode MOSFET A MOSFET built on a p-type substrate with n-type drain and source regions. An n-type channel is created in the p- substrate during conduction.
p-channel enhancement-mode MOSFET A MOSFET built on an n-type substrate with p-type drain and source regions. During conduction, a p-type channel is created in the n-substrate.
CMOS A logic family based on the switching of n- and p-channel (“complementary”) enhancement-mode MOSFETs.
All the logic circuits we have examined so far have been based on the switching of bipolar junction transistors. Another major logic family, CMOS, is based on the switching of metal-oxide-semiconductor field effect transistors, or MOSFETS.
There are two major types of MOSFETs, called depletion-mode and enhancementmode MOSFETs. We will concentrate on the enhancement-mode devices, as they are the type used in the manufacture of digital ICs. Details of the differences between depletionand enhancement-mode transistors can be found in any good textbook on electronic devices.
MOSFETs can be categorized in another way: as n-channel and p-channel devices, much as bipolar transistors are classified as NPN or PNP.
CMOS logic is constructed from both n- and p-channel MOSFETs. CMOS (“Complementary MOS”) refers to the opposite, or complementary, operation of n- and p-channel transistors.
MOSFET Structure
Figure 11.45 shows the structure and symbol of an n-channel enhancement-mode MOSFET in an integrated circuit. The device is built on a substrate of p-type silicon, which has a deficiency of electrons in its structure. The drain and source regions are “wells” of n-type silicon, which has an excess of electrons. The drain and source are roughly equivalent to the emitter and collector of a bipolar transistor.
FIGURE 11.45
n-Channel MOSFET
The substrate is shown as a terminal with an arrow. The arrow points in for an n- channel device and out for a p-channel device. In nearly all cases, the substrate is shorted to the source terminal. (Some exceptions to this general rule will be examined when we look at circuits of CMOS gates.)