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Embedded Systems Development and Labs; The English Edition

voice data transmission from the MSB (most significant bit) to the LSB (low significant bit). The MSB will always be transferred in the first clock period after the WS signal is toggled. If the data length does not match, the receiver or sender will automatically intercept or fill the data. For more information, please refer to the IIS specification presented in the ScC44BOX User’s Manual.

3. Circuit Design

1) S3C44B0 IIS

(1) Signal Lines

The IIS bus has five lines:

●Serial data input (IISDI): The SD signal line of the IIS bus. Input.

●Serial data output (IISDO): The SD signal line of the IIS bus. Output.

●Left/right channel select (IISLRCK): The WS signal line of the IIS bus. Sampling clock.

●Serial bit clock (IISCLK): The SCK signal line of the IIS bus.

●CODECLK is generally 256 (256fs) or 384 (384fs) times the sample frequency (fs). CLDELEK is obtained from the main CPU clock frequency. The CPU timer registers can be configured through programming. The value for the frequency division can be from 0 to 16.The relationship of CODECLK and sample frequency is shown is Table 6-1. It needs to correctly select the IISLRCK and CODEECLK.

Table 6-1 The Relationship of CODECLK and IISRCK

(2) Registers

There are three registers related to IIS:

●IIS Control Register IISCON. IISCON can access the FIFO ready flag, enable or disable transmit DMA service, enable IISLRCK, IIS prescaler and IIS interface.

●IIS Mode Register IISMOD. IISMOD can select master-slave mode, send-receive mode, active level, serial data bit per channel, select CODECLK and IISRCK.

●IIS Prescaler Register IISPSR.

(3) Data Transfer

Normal mode or DMA mode can be selected for data transferring. In normal mode, the microprocessor transfers data according to the status of FIFO. The microprocessor itself accomplishes the data transfer from FIFO to the IIS bus. The status of FIFO is available via IISFCON register. The data can be directly written into the FIFO register IISFIF. In DMA mode, the DMA controller completely controls the data transfer to/from FIFO. The DMA controller automatically sends/receives data according to the status of the FIFO.

2) UDA1341TS Chip

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Embedded Systems Development and Labs; The English Edition

The UDA1341TS is a voice CODEC made by Philips. UDA1341TS can convert analog dimensional stereo sound into digital signal and vise versa. It can process the analog signal using PGA (Programmable Gain Access) and AGC (Automatic Gain Control) functions. For digital signals, this chip also provides special DSP functions. UDA1341TS is widely used in MDs, CDs, Notebooks, PCs and Camcoders.

The UDA1341TS provides two groups of voice signal input lines, one group of signal output lines, one group of IIS bus interface lines, and one group of L3 bus lines.

The IIS bus interface lines include clock line BCK, word selection line WS, data input line DATAI, data output line DATAO and voice system clock SYSCLK.

The L3 bus lines includes microprocessor interface data line L3DATA, microprocessor interface mode line L3MODE, microprocessor interface clock line L3CLOCK. The microprocessor can configure the UDA1341TS voice processing parameters and system control parameters through the L3 bus. However, the S3C44B0X has no L3bus and the general I/O ports must be used to connect to the UDA1341TS L3 bus. For the L3 bus time sequence and control methods, please refer to UDA1341TS_datasheet.

3) Circuit Interconnection

The IIS interface circuit is shown in Figure 6-20.

IISLRC

WS

VOUT

SPEAK

VOUT

IISD

DAT

IISD

DATA

IISCL

BC

PA

L3DAT VINL

Micropho

DQM

L3MO

VINR

DQM

L3CLOCK

CODE

SYSCL

44B0

UDA1341

Figure 6-20 IIS Interface Circuit

262

// test record
// play wave 5 times // close IIS

Embedded Systems Development and Labs; The English Edition

Figure 6-20 IIS Interface Circuit

6.3.5 Sample Programs

/*--- function code---*/ /*******************************************************************

* name:

Test_Iis

* func:

Test IIS circuit

* para:

none

* ret:

none

*modify:

*comment:

********************************************************************/

void Test_Iis(void)

{

IISInit(); // initialize IIS

Uart_Printf(" press \"R\" to Record..., any key to play wav(t.wav)\n"); if(Uart_Getch()=='R')

Record_Iis(); Playwave(5); IISClose();

}

/*********************************************************************

* name:

IISInit

* func:

Initialize IIS circuit

* para:

none

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Embedded Systems Development and Labs; The English Edition

* ret:

none

*modify:

*comment:

********************************************************************/

void IISInit(void)

{

rPCONE = (rPCONE&0xffff)+(2<<16);

// Set I/O port PE8 output CODECLK signal

iDMADone = 0;

/* initialize philips UDA1341 chip */

Init1341(PLAY);

}

/********************************************************************

* name:

Init1341

* func:

Init philips 1341 chip

* para:

none

* ret:

none

*modify:

*comment:

******************************************************************/

void Init1341(char mode)

{

/* Port Initialize */

rPCONA = 0x1ff;

// set PA9 as output and connect to L3D

rPCONB = 0x7CF;

// set PG5:L3M connect to PG4:L3C

rPDATB = L3M|L3C;

// L3M=H(start condition),L3C=H(start condition)

/* L3 Interface */

_WrL3Addr(0x14+2);

// status (000101xx+10)

#ifdef FS441KHZ

_WrL3Data(0x60,0);

// 0,1,10,000,0 reset,256fs,no DCfilter,iis

#else

_WrL3Data(0x40,0);

// 0,1,00,000,0 reset,512fs,no DCfilter,iis

#endif

_WrL3Addr(0x14+2);

// status (000101xx+10)

#ifdef FS441KHZ

_WrL3Data(0x20,0);

// 0,0,10,000,0 no reset,256fs,no DCfilter,iis

#else

_WrL3Data(0x00,0);

// 0,0,00,000,0 no reset,512fs,no DCfilter,iis

#endif

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Embedded Systems Development and Labs; The English Edition

_WrL3Addr(0x14+2);

// status (000101xx+10)

_WrL3Data(0x81,0);

// 1,0,0,0,0,0,11 OGS=0,IGS=0,ADC_NI,DAC_NI,sngl speed,AonDon

_WrL3Addr(0x14+0);

// DATA0 (000101xx+00)

_WrL3Data(0x0A,0);

//record

if(mode)

{

_WrL3Addr(0x14+2); //STATUS (000101xx+10)

_WrL3Data(0xa2,0); //1,0,1,0,0,0,10 : OGS=0,IGS=1,ADC_NI,DAC_NI,sngl speed,AonDoff

_WrL3Addr(0x14+0); //DATA0 (000101xx+00)

_WrL3Data(0xc2,0); //11000,010

: DATA0, Extended addr(010)

_WrL3Data(0x4d,0); //010,011,01 : DATA0, MS=9dB, Ch1=on Ch2=off,

}

//record

}

/*******************************************************************

* name:

_WrL3Addr

* func:

write control data address to 1341 through L3-interface

* para:

data -- control data address

* ret:

none

*modify:

*comment:

********************************************************************/

void _WrL3Addr(U8 data)

{

U32 vPdata = 0x0;

// L3D=L

U32 vPdatb = 0x0;

// L3M=L(in address mode)/L3C=L

S32 i,j;

rPDATB = vPdatb;

// L3M=L

rPDATB |= L3C;

// L3C=H

for( j=0; j<4; j++ )

// tsu(L3) > 190ns

;

//PA9:L3D PG6:L3M PG7:L3C for( i=0; i<8; i++ )

{

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Embedded Systems Development and Labs; The English Edition

if( data&0x1 )

// if data bit is 'H'

{

rPDATB = vPdatb;

// L3C=L

rPDATA = L3D;

// L3D=H

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

rPDATB = L3C;

// L3C=H

rPDATA = L3D;

// L3D=H

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

}

else

// if data bit is 'L'

{

rPDATB = vPdatb;

// L3C=L

rPDATA = vPdata;

// L3D=L

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

rPDATB = L3C;

// L3C=H

rPDATA = vPdata;

// L3D=L

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

}

data >>= 1;

}

rPDATG = L3C|L3M;

// L3M=H,L3C=H

}

/*********************************************************************

* name:

_WrL3Data

* func:

write control data to 1341 through L3-interface

* para:

data -- control data

*halt -- halt operate

* ret:

none

*modify:

*comment:

******************************************************************/

void _WrL3Data(U8 data,int halt)

{

U32 vPdata = 0x0;

// L3D=L

U32 vPdatb = 0x0;

// L3M/L3C=L

S32 i,j;

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Embedded Systems Development and Labs; The English Edition

if(halt)

{

rPDATB = L3C;

// L3C=H(while tstp, L3 interface halt condition)

for( j=0; j<4; j++ )

// tstp(L3) > 190ns

;

}

rPDATB = L3C|L3M;

// L3M=H(in data transfer mode)

for( j=0; j<4; j++ )

// tsu(L3)D > 190ns

;

// PA9:L3MODE PG6:L3DATA PG7:L3CLOCK for( i=0; i<8; i++ )

{

if( data&0x1 )

// if data bit is 'H'

{

rPDATB = L3M;

// L3C=L

rPDATA = L3D;

// L3D=H

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

rPDATB = L3C|L3M;

// L3C=H,L3D=H

rPDATA = L3D;

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

}

else

// if data bit is 'L'

{

rPDATB = L3M;

// L3C=L

rPDATA = vPdata; // L3D=L

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

rPDATB = L3C|L3M;

// L3C=H

rPDATA = vPdata; // L3D=L

for( j=0; j<4; j++ )// tcy(L3) > 500ns

;

}

data >>= 1;

}

rPDATB = L3C|L3M;

// L3M=H,L3C=H

}

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