Файл: Embedded Systems Design - An Introduction to Processes Tools and Techniques (A. Berger, 2002).pdf

DC would tell you how many times it evaluates to TRUE and how many times it evaluates to FALSE. MCDC would also show you the logical conditions that lead to the decision outcome. Because you know that the if statement decision condi tion would evaluate to TRUE if A is TRUE AND B is also TRUE, MCDC would also tell you the states of A and B each time the decision was evaluated. Thus, you would know why the decision evaluated to TRUE or FALSE not just that it was TRUE or FALSE.

Hardware Instrumentation

Emulation memories, logic analyzers, and IDEs are potentially useful for testcoverage measurements. Usually, the hardware functions as a trace/ capture interface, and the captured data is analyzed offline on a separate computer. In addition to these three general-purpose tools, special-purpose tools are used just for performance and test coverage measurements.

Emulation Memory

Some vendors include a coverage bit among the attribute bits in their emulation memory. When a memory location is accessed, its coverage bit is set. Later, you can look at the fraction of emulation memory “hits” and derive a percent of coverage for the particular test. By successively “mapping” emulation memory over system memory, you can gather test-coverage statistics.

One problem with this technique is that it can be fooled by microprocessors with on-chip instruction or data caches. If a memory section, called a refill line, is read into the cache but only a fraction of it is actually accessed by the program, the coverage bit test will be overly optimistic in the coverage values it reports. Even so, this is a good upper-limit test and is relatively easy to implement, assuming you have an ICE at your disposal.

Logic Analyzer

Because a logic analyzer also can record memory access activity in real time, it’s a potential tool for measuring test coverage. However, because a logic analyzer is designed to be used in “trigger and capture” mode, it’s difficult to convert its trace data into coverage data. Usually, to use a logic analyzer for coverage measurements, you must resort to statistical sampling.

For this type of measurement, the logic analyzer is slaved to a host computer. The host computer sends trigger commands to the logic analyzer at random intervals. The logic analyzer then fills its trace buffer without waiting for any other trigger conditions. The trace buffer is uploaded to the computer where the memory addresses, accessed by the processor while the trace buffer was capturing data, are added to a database. For coverage measurements, you only need to know whether each memory location was accessed; you don’t care how many times an address was accessed. Thus, the host computer needs to process a lot of redundant data. For example, when the processor is running in a tight loop, the logic analyzer collects a lot of redundant accesses. If access behavior is sampled over long test runs (the test suite can be repeated to improve sampling accuracy), the sampled coverage begins to converge to the actual coverage.

Of course, memory caches also can distort the data collected by the logic analyzer. On-chip caches can mask coverage holes by fetching refill lines that were only partly executed. However, many logic analyzers record additional information

provided by the processor. With these systems, it’s sometimes possible to obtain an accurate picture of the true execution coverage by post-processing the raw trace. Still, the problem remains that the data capture and analysis process is statistical and might need to run for hours or days to produce a meaningful result.

In particular, it’s difficult for sampling methods to give a good picture of ISR test coverage. A good ISR is fast. If an ISR is infrequent, the probability of capturing it during any particular trace event is correspondingly low. On the other hand, it’s easy to set the logic analyzer to trigger on ISR accesses. Thus, coverage of ISR and other low-frequency code can be measured by making a separate run through the test suite with the logic analyzer set to trigger and trace just that code.

Software Performance Analyzers

Finally, a hardware-collection tool is commercially available that facilitates the lowintrusion collection method of hardware assist without the disadvantage of intermittent collection of a logic analyzer. Many ICE vendors manufacture hardware-based tools specifically designed for analyzing test coverage and software performance. These are the “Cadillac™” tools because they are specifically designed for gathering coverage test data and then displaying it in a meaningful way. By using the information from the linker’s load map, these tools can display coverage information on a function or module basis, rather than raw memory addresses. Also, they are designed to collect data continuously, so no gaps appear in the data capture, as with a logic analyzer. Sometimes these tools come already bundled into an ICE, others can be purchased as hardware or software add-ons for the basic ICE. These tools are described in more detail later in the following section: “Performance Testing.”

Performance Testing

The last type of testing to discuss in this chapter is performance testing. This is the last to be discussed because performance testing, and, consequently, performance tuning, are not only important as part of your functional testing but also as important tools for the maintenance and upgrade phase of the embedded life cycle. Performance testing is crucial for embedded system design and, unfortunately, is usually the one type of software characterization test that is most often ignored. Dave Stewart, in “The Twenty-Five Most Common Mistakes with Real-Time Software Development,”[9] considers the failure to measure the execution time of code modules the number one mistake made by embedded system designers.

Measuring performance is one of the most crucial tests you need to make on your embedded system. The typical response is that the code is “good enough” because the product works to specification. For products that are incredibly cost sensitive, however, this is an example of engineering at its worst. Why overdesign a system with a faster processor and more and faster RAM and ROM, which adds to the manufacturing costs, lowers the profit margins, and makes the product less competitive, when the solution is as simple as finding and eliminating the hot spots in the code?

On any cost-sensitive embedded system design, one of the most dramatic events is the decision to redesign the hardware because you believe you are at the limit of performance gains from software redesign. Mostly, this is a gut decision rather than a decision made on hard data. On many occasions, intuition fails. Modern software, especially in the presence of an RTOS, is extremely difficult to fully unravel and understand. Just because you can’t see an obvious way to improve the system throughput by software-tuning does not imply that the next step is a

hardware redesign. Performance measurements made with real tools and with sufficient resources can have tremendous payback and prevent large R&D outlays for needless redesigns.

How to Test Performance

In performance testing, you are interested in the amount of time that a function takes to execute. Many factors come into play here. In general, it’s a nondeterministic process, so you must measure it from a statistical perspective. Some factors that can change the execution time each time the function is executed are:

Contents of the instruction and data caches at the time the function is entered

RTOS task loading

Interrupts and other exceptions

Data-processing requirements in the function

Thus, the best you can hope for is some statistical measure of the minimum, maximum, average, and cumulative execution times for each function that is of interest. Figure 9.3 shows the CodeTEST performance analysis test tool, which

instrumentation tags will help uncoverAmemory leakages and fragmentation problems while they are occurring. This is infinitely preferable to dealing with a

nonreproducible system lock-up once every two or three weeks. Figure 9.2 shows one such memory management test tool.

Figure 9.2: Memory management test tool.

The CodeTEST memory management test program (courtesy of Applied Microsys tems Corporation).

Team-Fly®

Figure 9.3: CodeTEST test tool.

CodeTEST performance analysis tool display showing the minimum, maximum, average, and cumulative execution times for the functions shown in the leftmost column (courtesy of Applied Microsystems Corporation).

From the Trenches

Performance testing and coverage testing are not entirely separate activities. Coverage testing not only uncovers the amount of code your test is exercising, it also shows you code that is never exercised (dead code) that could easily be eliminated from the product. I’m aware of one situation in which several design teams adapted a linker command file that had originally been written for an earlier product. The command file worked well enough, so no one bothered to remove some of the extraneous libraries that it pulled in. It wasn’t a problem until they had to add more functionality to the product but were limited to the amount of ROM space they had. Thus, you can see how coverage testing can provide you with clues about where you can excise code that does not appear to be participating in the program. Although removing dead code probably won’t affect the execution time of the code, it certainly will make the code image smaller. I say probably because on some architectures, the dead code can force the compiler to generate more time-consuming long jumps and branches. Moreover, larger code images and more frequent jumps can certainly affect cache performance.

Conceptually, performance testing is straightforward. You use the link map file to identify the memory addresses of the entry points and exit points of functions. You then watch the address bus and record the time whenever you have address matches at these points. Finally, you match the entry points with the exit points, calculate the time difference between them, and that’s your elapsed time in the function. However, suppose your function calls other functions, which call more functions. What is the elapsed time for the function you are trying to measure? Also, if interrupts come in when you are in a function, how do you factor that information into your equation?

Fortunately, the commercial tool developers have built in the capability to unravel even the gnarliest of recursive functions.

Hardware-based tools provide an attractive way to measure software performance. As with coverage measurements, the logic analyzer can be programmed to capture traces at random intervals, and the trace data — including time stamps — can be post-processed to yield the elapsed time between a function’s entry and exit points. Again, the caveat of intermittent measurements applies, so the tests might have to run for an extended period to gather meaningful statistics.

Hardware-only tools are designed to monitor simultaneously a spectrum of function entry points and exit points and then collect time interval data as various functions are entered and exited. In any case, tools such as these provide unambiguous information about the current state of your software as it executes in real time.

Hardware-assisted performance analysis, like other forms of hardwareassisted measurements based on observing the processor’s bus activity, can be rendered less accurate by on-chip address and data caches. This occurs because the appearance of an address on the bus does not necessarily mean that the instruction at that address will be executed at that point in time, or any other point in time. It only means that the address was transferred from memory to the instruction cache.

Tools based on the instrumentation of code are immune to cache-induced errors but do introduce some level of intrusion because of the need to add extra code to produce an observable tag at the function’s entry points and exit points. Tags can be emitted sequentially in time from functions, ISRs, and the RTOS kernel itself.

With proper measurement software, designers can get a real picture of how their system software is behaving under various system-loading conditions. This is exactly the type of information needed to understand why, for example, a functional test might be failing.

From the Trenches

From personal experience, the information, which these tools provide a design team, can cause much disbelief among the engineers. During one customer evaluation, the tool being tested showed that a significant amount of time was being spent in a segment of code that none of the engineers on the project could identify as their software.

Upon further investigation, the team realized that in the build process the team had inadvertently left the compiler switch on that included all the debug information in the compiled code. Again, this was released code. The tool was able to show that they were taking a 15-percent performance hit due to the debug code being present in the released software. I’m relatively certain that some heads were put on the block because of this, but I wasn’t around to watch the festivities.

Interestingly, semiconductor manufacturers are beginning to place additional resources on-chip for performance monitoring, as well as debugging purposes. Desktop processors, such as the Pentium and AMD’s K series, are equipped with performance-monitoring counters; such architectural features are finding their way into embedded devices as well. These on-chip counters can count elapsed time or other performance parameters, such as the number of cache hits and cache misses.

Another advantage of on-chip performance resources is that they can be used in conjunction with your debugging tools to generate interrupts when error conditions occur. For example, suppose you set one of the counters to count down to zero when a certain address is fetched. This could be the start of a function. The counter counts down; if it underflows before it’s stopped, it generates an interrupt or exception, and processing could stop because the function took too much time. The obvious advantages of onchip resources are that they won’t be fooled by the presence of on-chip caches and that they don’t add any overhead to the code execution time. The downside is that you are limited in what you can measure by the functionality of the on-chip resources.

Maintenance and Testing

Some of the most serious testers of embedded software are not the original designers, the Software Quality Assurance (SWQA) department, or the end users. The heavy-duty testers are the engineers who are tasked with the last phases of the embedded life cycle: maintenance and upgrade. Numerous studies (studies by Dataquest and EE Times produced similar conclusions) have shown that more than half of the engineers who identify themselves as embedded software and firmware engineers spend the majority of their time working on embedded systems that have already been deployed to customers. These engineers were not the original designers who did a rotten job the first time around and are busy fixing residual bugs; instead, these engineers take existing products, refine them, and maintain them until it no longer makes economic sense to do so.

One of the most important tasks these engineers must do is understand the system with which they’re working. In fact, they must often understand it far more intimately than the original designers did because they must keep improving it without the luxury of starting over again.

From the Trenches

I’m often amused by the expression, “We started with a clean sheet of paper,” because the subtitle could be, “And we didn’t know how to fix what we already had.” When I was an R&D Project Manager, I visited a large telecomm vendor who made small office telephone exchanges (PBX). The team I visited was charged with maintaining and upgrading one of the company’s core products. Given the income exposure riding on this product, you would think the team would have the best tools available. Unfortunately, the team had about five engineers and an old, tired PBX box in the middle of the room. In the corner was a dolly with a four-foot high stack of source code listings. The lead engineer said someone wheeled that dolly in the previous week and told the team to “make it 25 percent better.” The team’s challenge was to first understand what they had and, more importantly, what the margins were, and then they could undertake the task of improving it 25 percent, whatever that meant. Thus, for over half of the embedded systems engineers doing embedded design today, testing and understanding the behavior of existing code is their most important task.

It is an unfortunate truth of embedded systems design that few, if any, tools have been created specifically to help engineers in the maintenance and upgrade phases of the embedded life cycle. Everyone focuses on new product development. Go to any Embedded Systems Conference™, and every booth is demonstrating something to help you improve your time to market. What if you’re already in the market? I’ve been to a lot of Embedded System Conferences™ and I’ve yet to have anyone tell me his product will help me figure out what I’m already shipping to customers. Today, I’m aware of only one product idea that might come to market for a tool specifically focusing on understanding and categorizing existing embedded software in a deployed product.

Additional Reading

Barrett, Tom. “Dancing with Devils: Or Facing the Music on Software Quality.” Supplement to Electronic Design, 9 March 1998, 40.

Beatty, Sean. “Sensible Software Testing.” Embedded Systems Programming, August 2000, 98.

Myers, Glenford J. The Art of Software Testing. New York: Wiley, 1978.

Simon, David. An Embedded Software Primer. Reading, MA: AddisonWesley, 1999.

Summary

In a way, it’s somewhat telling that the discussion of testing appears at the end of this book because the end of the product development cycle is where testing usually occurs. It would be better to test in a progressive manner, rather than waiting until the end, but, for practical reasons, some testing must wait. The principal reason is that you have to bring the hardware and software together before you can do any kind of meaningful testing, and then you still need to have the real-world events drive the system to test it properly.

Although some parts of testing must necessarily be delayed until the end of the development cycle, the key decisions about what to test and how to test must not be delayed. Testability should be a key requirement in every project. With modern SoC designs, testability is becoming a primary criterion in the processor-selection process.

Finally, testing isn’t enough. You must have some means to measure the effectiveness of your tests. As Tom DeMarco[3], once said, “You can’t control what you can’t measure.”

If you want to control the quality of your software, you must measure the quality of your testing. Measuring test coverage and performance are important components but for safety critical projects, even these aren’t enough.

Works Cited

1.Hopper, Grace Murray. “The First Bug.” Annals of the History of Computing, July 1981, 285.

2.Horning, Jim. ACM Software Engineering Notes. October 1979, 6.

3.DeMarco, Tom. Controlling Software Projects. New York: Yourdon, 1982.

4.Leveson, Nancy and Clark S. Turner. “An Investigation of the Therac-25 Accidents.” IEEE Computer, July 1993, 18–41.

5.Main, Jeremy. Quality Wars: The Triumphs and Defeats of American Business. New York: Free Press, 1994.

6.Myers, Glenford J. The Art of Software Testing. New York: Wiley, 1978.

7.Ross, K.J. & Associates.

http://www.cit.gu.edu.au/teaching/CIT2162/991005.pdf , p. 43.

8.Simon, David. An Embedded Software Primer. Reading, MA: AddisonWesley, 1999.

9.Stewart, Dave. “The Twenty-Five Most Common Mistakes with RealTime Software Development.” A paper presented at the Embedded Systems Conference, San Jose, 26 September 2000.

Chapter 10: The Future

The previous chapters have focused on tools and techniques that you need to do your job today. This chapter looks beyond the job as it is today to the future. First, I want to describe a new technology — reconfigurable hardware — that has the potential to completely redefine the process of creating an embedded system.

The closing half of this chapter is devoted not so much to what might come, as to what I heartily wish would come.

Reconfigurable Hardware

The ultimate solution to the partitioning problem might be a new technology known as reconfigurable hardware. Reconfigurable hardware might be the future of computing systems in general, whether they are desktop PCs or embedded systems. Reconfigurable hardware is circuitry that can be changed dynamically so that its very structure changes at run time.

Imagine, for example, a microcontroller that consists of a standard microprocessor core, a big block of this reconfigurable hardware, and nothing else. Unlike current SoC solutions, this imaginary part wouldn’t include any dedicated peripheral devices, such as timers, parallel ports, serial ports, Ethernet ports, and so on. Instead, when the application calls for a parallel port, part of the reconfigurable logic would be configured to be a parallel port. If a serial port is needed, the same thing happens. If the design requires high-speed data steering logic, as you might find in a telecommunications application, the hardware block is reconfigured to be a steering block.

What is this magic hardware? The basis of this “brave new world” of computing hardware is a device that has been around for more than 10 years, the Field Programmable Gate Array (FPGA). Figure 10.1 shows a conceptual model of an FPGA. The device consists of the following:

Figure 10.1: FPGA.

Conceptual diagram of an FPGA.

A “sea of gates,” such as general purpose AND gates, OR gates, NOT gates, and EXCLUSIVE OR gates

A matrix of programmable interconnection elements

General-purpose memory

General-purpose registers

A configuration memory that, when programmed, connects the devices into the desired circuit blocks