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The digital code produced by the ADC will be correct and not contain any error when the analog input voltage corresponds exactly with a quantised voltage level. However, the ADC will incur an error known as quantisation error, when the input voltage is not exactly equal to the nearest quantised voltage level. For example, referring to Figure 11-2; zero quantisation error occurs when the analog input is equal to 0V, 0.5V, 1.0V, etc. The quantisation error is a maximum (equal to ½ a quantisation level) when the analog input voltage lies halfway between two quantisation levels – 0.25V for the previous example.

Another type of error can occur with analog-to-digital conversion, known as monotonic error. If the input voltage to the converter increases in discrete quantised levels, the digital output code should also increase by the same number of increments. If this does not happen, then monotonic error has occurred, reducing the useful resolution of the converter.

The digital output code from an ADC is produced in either serial or parallel format. The converter shown in Figure 11-1 uses parallel format with all 8 output bits available. Parallel output converters usually have faster operating times than the serial output types but require additional connections to the digital system. However, ADCs with serial output require more work to control than parallel output types. Some converters contain an internal analog multiplexer, allowing multiple analog input channels to be processed (at a proportionately slower speed).

At the start of the conversion process the input voltage must be sensed by the converter’s input stage circuitry. The output impedance of the external circuit that is providing the input signal to the ADC must be sufficiently low compared to the ADC’s input impedance for the ADC to function properly. The converter will operate over a limited range of input voltage, and this too must be considered when scaling the source of input voltage before connecting it to the ADC.

11.3 Conversion Techniques

Several popular analog-to-digital conversion techniques are implemented with electronic circuitry including voltage-to-frequency converters, single slope ADC, dual slope ADC, successive approximation ADC, and flash ADC. Some converters use a combination of methods to take advantage of the independent benefits of each approach. For example, the high-speed flash technique is combined with successive approximation to produce a ‘low cost’ but very fast converter. The voltage-to-frequency technique has been mentioned previously (Chapter 10) and is not normally considered for use, due to its relatively slow speed. The other converter techniques are widely used and are explained as follows.

Single Slope ADC

This converter uses a constant current source charging a capacitor, a voltage comparator, and a counter with clock source and control logic as shown in Figure 11-3.

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Digital Output

Code

Figure 11-3 Simplified single slope ADC.

The conversion process begins immediately after the ‘Start Conversion’ input is driven to its active state and proceeds in two stages as follows:

Stage 1 - Initialisation

The discharging switch across capacitor C closes (activated by the control logic), discharging the capacitor to zero volts. Next the counter is reset to a value of zero, the counter logic opens the switch, and counting commences.

Stage 2 - Integration

The constant current source drives current into capacitor C, generating a ramping voltage at the comparator +ve input (this process is known as integration). When this ramping voltage exceeds the positive input voltage (VIN) present on the comparator –ve input, the comparator will toggle state from low to high. This change in state of the comparator will signal the counter logic to cease counting, at which time conversion is complete. The ‘Conversion Complete’ output pin will then be switched to its active state to indicate end of conversion to external devices. The counter output code will now represent the analog input voltage. A larger magnitude of input voltage will require a longer time period for the ramping voltage to reach its level, producing a larger digital output value.

The cycle described as Stage 1 and 2 will repeat when the next ‘Start Conversion’ pulse arrives.

The conversion speed of the single slope ADC is relatively slow although its accuracy is reasonably good, being affected by the long-term stability of the counter’s clock, the stability of the constant current source, and the quality of the

336 11 ANALOG-TO-DIGITAL CONVERSION

capacitor, ideally having low dielectric absorption. When capacitors with high dielectric absorption are discharged and then removed from the discharging circuit, some charge will remain stored inside the capacitor on polarised dielectric interfaces. This charge generates an unwanted error voltage. Capacitors with very low dielectric absorption will have negligible voltage across them after being discharged. A further advantage of the single slope converter is that noise on the input voltage signal is averaged out during the process of integration.

Dual Slope ADC

This converter is similar to the single slope ADC except that two ramping stages are employed during conversion to greatly improve accuracy. Figure 11-4 shows the block diagram for such a converter.

Digital Output

Code

Figure 11-4 Simplified dual slope ADC.

Once the ‘Start Conversion’ input is asserted, the conversion process will proceed in three stages as follows:

Stage 1 – Initialisation

The ADC is ‘zeroed’ by closing SW2 to fully discharge the integrating capacitor C to zero volts.

Stage 2 – Integrate Up using ‘VIN’

At the start of this stage the counter is reset to a count of zero, and SW1 is set to position 1, connecting the input voltage (VIN) to the voltage-controlled current source. SW2 is opened, allowing the current source, controlled by the input voltage signal VIN, to charge the integration capacitor C, producing an upwards ramping voltage shown as ‘A’ in Figure 11-5. The ramping is

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allowed to proceed for a fixed time period (usually the maximum count value of the counter – to maximise conversion accuracy). At the end of this time period, the counter is reset to a count of zero and the final stage of conversion will begin.

Stage 3 – Integrate Down using ‘Reference Voltage’

SW1 is moved to position 2, allowing the precise negative reference voltage to control the current source. This produces a negative current of constant value, which progressively discharges capacitor C until the voltage at the comparator +ve input falls just below the ground potential (0V) connected to the comparator’s –ve input. When this occurs the comparator output changes state and stops the counter. The count value reached during this stage represents the analog input voltage (VIN), being proportional to its magnitude.

Figure 11-5 shows the voltage waveform generated during the two integration stages. The lower set of rising and falling voltages across the capacitor shown as ‘C’ and ‘D’ are generated when the input voltage VIN is a lower value. Note that the down ramping voltages marked as ‘B’ and ‘D’ have the same slope since they are generated by a constant current of the same value (controlled by VREF).

Figure 11-5 Dual slope ADC voltage waveform.

The advantage of the dual slope ADC compared with the single slope converter is its improved accuracy, largely determined by the stability of the reference voltage. Unlike the single slope ADC, the dual slope ADC is not affected by any long-term drift in clock frequency since the same clock is used for timing Stage 2 and Stage 3. The dual slope ADC shares similar noise immunity characteristics as the single slope converter and requires the use of a good quality capacitor with low dielectric absorption. This converter is relatively slow but very accurate – up to around 18-bit resolution. Other converters cannot match this converter for accuracy at low cost and this is one of the reasons it is widely used in instruments such as precision digital multimeters.

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Successive Approximation ADC

This converter is very popular due to its relatively fast conversion speed, good accuracy and low cost. Figure 11-6 shows the block diagram for this converter.

DAC

Conversion

Code

Digital Output

Figure 11-6 Simplified successive approximation ADC.

Conversion begins immediately after the ‘Start Conversion’ input is driven to its active state and proceeds as follows:

Stage 1 – Initialisation

The control logic clears all control logic output bits. Stage 2 – Successive Approximation Process

The converter digital output code is formed sequentially during a series of tests, where the analog input voltage is compared against the analog value of a digital code, this code constructed during the conversion cycle itself.

Each bit value is tested sequentially against the analog input voltage, starting with the most significant bit (MSB). For example, using an 8-bit converter, the digital test code would be 1000 0000, representing half the quantised voltage range. This code is fed to the input of the digital-to-analog converter (DAC), producing the analog voltage VDAC. Voltage VDAC is tested against voltage VIN using the comparator. If VIN is greater in magnitude than VDAC, the comparator output will be HIGH and the control logic will keep the current bit, in this case the MSB and the output code would then be