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11 ANALOG-TO-DIGITAL CONVERSION 345

voltage. The time taken for the voltage across the capacitor to ‘reach’ the input voltage (within limits) is referred to as the acquisition time.

Stage 2 – Holding Sampled Voltage

At the end of the sampling period, the ‘Sample Command’ is toggled to the ‘Hold’ state to store the sampled signal for the ADC input. Unfortunately there is a delay in opening the analog switch known as aperture delay. This delay causes the output of the sample and hold (S/H) to follow the input voltage for the aperture delay time period, creating an error in sampled voltage and hence possible errors in the digital code produced by the ADC. The ADC conversion commences during the hold period that follows the sampling process.

Ideally the output of the sample and hold (S/H) remains fixed in amplitude over the entire ADC conversion interval. In practice the S/H output drops over time producing what is known as voltage droop. The droop occurs as charge stored on the capacitor is lost during the hold period, drawn into the neighbouring S/H circuitry connected to the capacitor, and also lost through the capacitor itself.

Aliasing

When sampling a repetitive waveform, it is possible to produce various sets of data values depending on the sample rate as shown in Figure 11-13 to Figure 11-15. Considering a sinusoidal waveform; should the sample rate be less than half the signal cycle or period, then a waveform similar to that shown in Figure 11-13 will be reconstructed from the data values produced by sampling and conversion. The reconstructed signal has a different frequency from the original sampled signal and is termed an alias signal. Beware: in this case the alias signal has the same amplitude and sinusoidal shape as the input signal and can be mistaken to be a proper representation of the actual input signal.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-13 Aliased reconstruction – sample rate too low.

Note: triangular-shaped waveforms will be reconstructed from digitised samples made at twice the signal frequency as shown in Figure 11-14. These reconstructed waveforms will have different amplitude depending on the position in the cycle

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when sampling begins.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-14 Digitising sample rate at 2 samples/signal cycle.

As the sample rate increases, the reconstructed waveform starts to resemble the original signal as shown in Figure 11-15.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-15 Digitising sample rate approximately 5 samples/signal cycle.

Real and Equivalent Time Sampling

All waveforms shown above have been sampled in real-time, meaning that data points are collected and stored sequentially as they are digitised. Repetitive signals of high frequency can be sampled and reconstructed using equivalent time sampling, where groups of sample sets are stored in memory and then used to generate complete waveform reconstruction. The resultant constructed waveform represents the originally sampled signal as shown in Figure 11-16. This technique is often utilised in digital oscilloscopes. When the user sets the oscilloscope timebase to sample high-speed repetitive waveforms, equivalent time sampling is used to create a pseudo sampling rate much greater than that of the oscilloscope’s digitiser.

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Input Signal and

Sampling Points

Digitised Waveform Reconstructed using

Sequential Equivalent Time Sampling

Figure 11-16 Equivalent time sampling.

Equivalent time sampling cannot be applied to the digitisation process when working with non-repetitive signals as shown in Figure 11-17. Instead, these signals need to be sampled and stored at a sufficiently high rate to provide enough detail in the reconstructed signal. Under these conditions many digital oscilloscopes are often challenged to provide adequate sampling rate and sufficient high-speed memory to store the digitised data. These two factors have a significant influence on the price of digital oscilloscopes.

Input Signal and

Sampling Points

Digitised

Waveform

Reconstructed

Figure 11-17 Real-time sampling of a non-repetitive waveform.

11.5 An Object Class for the ADC

In the last few chapters we learnt to design object classes to suit various objects such as the parallel port, the DAC, motors and the VCO. In a similar manner we can develop a software object for the ADC. The principle purpose of an analog-to- digital converter is to convert an analog voltage applied at its input to an integer bit number that can be read by the computer.

The conversion process for most analog-to-digital converters involves the following steps:

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1.Start an analog-to-digital conversion.

2.Wait for the conversion to complete.

3.Read the converted data.

Some analog-to-digital converter subsystems have a multiplexed analog input (i.e. more than one analog input where only one analog input is switched to the ADC at any given time). In such cases the above set of steps must be preceded by a “Select Input Channel” operation. The ADC used with our interface board does not have a multiplexer to use with multiple analog input channels. Therefore, we will not need to incorporate channel selection.

We must design our object class to have a member function to implement the steps listed above. The ADC on the interface board is designed to communicate through the parallel port. Therefore, the ParallelPort object forms an ideal base class for the new ADC class.

The ADC class needs to have only one private data member to store the digital value read from the ADC. Apart from the constructors, the ADC class must have a function to carry out the analog-to-digital conversion and store the resulting digital value into the private data member. A function is also needed to provide access to this private data member. A class definition that encapsulates this data and functions is given in Listing 11-1.

Listing 11-1 The header file for the ADC class – adc.h.

#ifndef AdcH #define AdcH

#include "pport.h"

class ADC : public ParallelPort

{

private:

unsigned char ADCValue;

public:

ADC(int baseaddress=0x378); unsigned char ADConvert(); unsigned char GetADCValue();

};

#endif

The function ADConvert() is the most involved of the three functions and is discussed first. We must decide which parts of the parallel port will be used and their purpose before before being able to write the C++ statements for this function.

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Figure 11-18 shows a block diagram of the ADC0804 with its input pins (on the left side) and output pins. The pin labels and descriptions are given in Table 11-2. These labels are used on the schematic diagram and can also be found near the ADC on the interface board.

Figure 11-18 ADC0804 block diagram.

Table 11-2 Interface pins of the ADC.

†Pin labels with a prefix of ‘/’ are active low.

The dots marking the Input and Output columns of Table 11-2 identify each signal as an input or an output with reference to the ADC. Now we need to evaluate a means of interfacing these signals to the parallel port.

Operation of signals

The voltage signal to be converted by the ADC is connected to its analog input pin labelled VIN. For testing purposes we can generate a suitable analog input voltage for the ADC using either the on-board potentiometer, the thermistor circuit, or the DAC operating in unipolar mode (jumper fitted across the header position marked LINK1).

The ADC’s input pins are configured as follows. The chip select pin (/CS) must be at logic-low for the ADC to operate. The read enable pin (/READ) must be held logic-low to enable reading the digital data from the ADC. The chip select signal is typically generated by the address decoding circuit of a hardware system that has several devices sharing a data bus. The interface board does not share a data bus, so

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we can permanently activate the above two signals; i.e. connect them directly to GND. This reduces the number of signals we need to interface with the parallel port.

The computer must control the start conversion signal connected to the start conversion pin (/START C.). An analog-to-digital conversion is initiated by applying an active-low pulse to this pin. We can generate an active-low pulse by driving a high-level signal momentarily to a low-level, returning the signal to a high state.

Immediately after the ADC completes its conversion operation, the data valid pin (/DATA VALID) will produce a brief low-level pulse. Since this low-level pulse is short in duration, it may not be possible to detect it and therefore determine the precise moment conversion was completed. Typically, this pulse is latched using hardware to ensure that a program will reliably detect the end of conversion. The electronic circuitry on the interface board has been kept to a minimum and as such does not include a latch circuit. Therefore, our best option is to allow sufficient time for the conversion to complete before reading the digital data. In addition, using this approach will free us from the need to interface the /DATA VALID signal.

Configuration of Port data bits to interface the ADC

We now need to assign the data bits that will interface the ADC to the parallel port. When using the ADC it is possible that the DAC will be used to provide programmable input voltages to the ADC. We will assume this to be the case when allocating our data bits. The digital input and output requirements for the ADC and DAC are shown in Table 11-3.

Table 11-3 DAC & ADC digital input and output pins.

Digital Inputs to the DAC: The eight digital input pins to the DAC need to be driven by parallel port output signals. Therefore, it makes sense to use output data bits (D0 to D7) of the port at address BASE to drive the DAC inputs (D0 to D7).