Файл: Microcontroller based applied digital control (D. Ibrahim, 2006).pdf
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70 THE PIC MICROCONTROLLER
following conditions must be met:
The global interrupt flag in INTCON must be enabled (GIE = 1).
The interrupt flag of the interrupting source in INTCON must be enabled (e.g. INTE = 1 to enable INT external interrupts).
Interrupt must physically occur (e.g. INT pin is raised to logic 1 if INTEDG was previously set to logic 1).
After an interrupt is detected the program jumps to the interrupt service routine which is at address 4 of the program memory. At this point further interrupts are disabled and the interrupt flag of the interrupt source (e.g. bit INTF of INTCON for external interrupts) must be cleared for a new interrupt to be accepted from the interrupting source.
3.3.1.3 TRISA and Port A Registers
Port A is a 5-bit-wide port with pins RA0–RA4, and at address 5 of the RFM. Four low-order bits (RA0–RA3) have CMOS output drivers with 25 mA current sink and source capabilities. RA4 is an open-drain port and a suitable pull-up resistor must be connected when used as an output port. Port A pins are bidirectional and the direction of a pin is determined by the settings of register TRISA. Setting a bit in TRISA makes the corresponding port A pin an input. Similarly, clearing a bit in TRISA makes the corresponding port A pin an output. For example, to make bits 0, 1 and 2 of port A input and the other bits output, we have to load TRISA register with:
00000111
3.3.1.4 TRISB and Port B Registers
Port B is a 8-bit-wide port with pins RB0–RB7, and at address 6 of the RFM. The pins have CMOS output drivers with 25 mA current sink and source capabilities. Pin RB0 can be used as an external interrupt pin. Similarly, pins RB4–RB7 can be used to generate an interrupt when the state of any of these pins changes. Port B pins are bidirectional, and the direction of a pin is determined by the settings of register TRISB. Setting a bit in TRISB makes the corresponding port B pin an input. Similarly, clearing a bit in TRISB makes the corresponding port B pin an output. For example, to make bits 0, 2 and 4 of port B input and the other bits output, we have to load TRISB register with:
00010101
3.3.1.5 TMR0 Register
The PIC16F84 provides an 8-bit timer, called TMR0, which can be used either as a timer or a counter. The structure of this timer is shown in Figure 3.17. When used as a counter, the register increments each time a clock pulse is applied to external pin T0CK1 of the microcontroller.
SOME POPULAR PIC MICROCONTROLLERS |
71 |
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F/4 |
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0 |
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T0CK1 |
1 |
1 |
T0IF |
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TMR0 |
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Pre-scaler |
0 |
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TOCS |
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PS2 PS1 PS0 |
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PSA |
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Figure 3.17 |
TMR0 structure |
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When used as a timer, the register increments at a rate determined by the microcontroller clock frequency and a pre-scaler, selected by register OPTION REG. The pre-scaler values range from 1 : 2 to 1 : 256. For example, when using a 4 MHz clock, the basic instruction cycle is 1 µs (a 4 MHz clock has a period of 0.25 µs, but the clock is internally divided by 4 to obtain the basic instruction cycle). If we select a pre-scaler rate of 1 : 8, the timer register will be incremented at every 8 µs.
A timer overflow interrupt is generated when the timer register overflows from 255 to 0. This interrupt can be enabled in software by setting bit 5 of the INTCON register. For example, if we wish to generate interrupts at 200 µs intervals with a 4 MHz clock, we can select a pre-scaler value of 1 : 4 and enable timer interrupts. The effective timer clock rate will then be 4 µs. For a time-out of 200 µs, we have to send 200/4 = 50 clock pulses to the timer register. Thus, the timer register TMR0 should be loaded with 256 − 50 = 206, i.e. a count of 50 before a timer overflow occurs.
The PIC16F84 microcontroller contains a 64-byte nonvolatile EEPROM memory, controlled by registers EEDATA, EEADR, EECON1 and EECON2. There are instructions to read and write the contents of this memory. EEPROM memory is usually used to store configuration data or maximum and minimum data obtained in real-time measurements.
The PIC16F84 microcontroller also contains a configuration register whose bits can be set or cleared during the programming of the device. This register contains bits to select the oscillator mode, to enable or disable code protection, to enable or disable the power-on timer, and to enable or disable the watchdog timer.
3.3.2 PIC16F877 Microcontroller
The PIC16F877 is a 40-pin popular PIC microcontroller. The device offers the following features:
8192 × 14 words flash program memory;
256 × 8 bytes of EEPROM data memory;
368 × 8 RAM data memory;
eight 10-bit A/D channels;
33 bidirectional I/O pins;
two 8-bit and one 16-bit timers;
72 THE PIC MICROCONTROLLER
13 |
OSC1/CLKIN |
RB0/INT |
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14 |
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OSC2/CLKOUT |
RB1 |
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1 |
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RB2 |
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MCLR/Vpp/THV |
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2 |
RB3/PGM |
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RA0/AN0 |
RB4 |
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3 |
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RA1/AN1 |
RB5 |
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4 |
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RA2/AN2/VREF− |
RB6/PGC |
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5 |
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RA3/AN3/VREF+ |
RB7/PGD |
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6 |
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RA4/T0CK1 |
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7 |
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RA5/AN4/SS |
RC0/T1OSO/T1CK1 |
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8 |
RC1/T1OSI/CCP2 |
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RC2/CCP1 |
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RE0/AN5/RD |
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9 |
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RC3/SCK/SCL |
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RE1/AN6/WR |
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10 |
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RE2/AN7/CS |
RC4/SDI/SDA |
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RC5/SDO |
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RC6/TX/CK |
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RC7/RX/DT |
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RD0/PSP0 |
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RD1/PSP1 |
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RD2/PSP2 |
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RD3/PSP3 |
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RD4/PSP4 |
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RD5/PSP5 |
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RD6/PSP6 |
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RD7/PSP7 |
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Figure 3.18 PIC16F877 pin configuration
33
34
35
36
37
38
39
40
15
16
17
18
23
24
25
26
19
20
21
22
27
28
29
30
watchdog timer;
14 interrupt sources;
capture, compare and PWM modules;
on-chip USART;
25 mA current source and sink capability.
Figure 3.18 shows the pin configuration of the PIC16F877. I/O ports are accessed as in the PIC16F84 where each port has a direction register (TRIS) which determines the mode of the I/O pins. One of the nice features of the PIC16F877 is that it contains a multiplexed eightchannel A/D converter with 10-bit resolution. A/D conversion is important in microcontroller based control applications, and the operation of this module is described in more detail below.
3.3.2.1 A/D Converter
The eight A/D converter inputs are named AN0–AN7 and are shared with PORTA and PORTE digital inputs as shown in Figure 3.19. There is only one A/D converter and the analog inputs are multiplexed where only one analog input data is converted to digital at any time. Analog
SOME POPULAR PIC MICROCONTROLLERS |
73 |
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AN7 |
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AN6 |
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AN5 |
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AN4 |
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A/D |
AN3 |
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converter |
AN2 |
|
AN1 |
||
AN0 |
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CHS2:CHS0
Figure 3.19 A/D converter block diagram
inputs can directly be applied to these inputs and the A/D converter generates 10-bit digital signals. The A/D module has four registers:
A/D result high register (ADRESH);
A/D result low register (ADRESL);
A/D control register0 (ADCON0);
A/D control register1 (ADCON1).
The bit definitions of the ADCON0 register are shown in Figure 3.20. This register controls the operation of the A/D converter. The conversion frequency, A/D channels, the A/D status and the conversion command are set by this register.
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
ADCS1 |
ADCS0 |
CHS2 |
CHS1 |
CHS0 |
GO/DONE |
– |
ADON |
Bit 7-6: ADSC1:ADSC0 A/D converter clock selection 00: fosc/2
01: fosc/8
10:fosc/32
11:frc
Bit 5-3: CHS2:CHS0 analog channel select bits 000: Select channel 0 (AN0)
001: Select channel 1 (AN1) 010: Select channel 2 (AN2) 011: Select channel 3 (AN3)
100:Select channel 4 (AN4)
101:Select channel 5 (AN5)
110:Select channel 6 (AN6)
111:Select channel 7 (AN7)
Bit 2: GO/DONE A/D conversion status bit
1: A/D conversion in progress (setting it starts the A/D conversion)
0: A/D converter not in progress (cleared by hardware when conversion is complete)
Bit 1: Not used
Bit 0: A/D on bit
1: A/D module is operating 0: A/D module is shut
Figure 3.20 ADCON0 bit definitions
74 |
THE PIC MICROCONTROLLER |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
ADFM |
– |
– |
– |
PCFG3 |
PCFG2 |
PCFG1 |
PCFG0 |
|
Bit 7: ADFM A/D result format
1: Right-justified. Six most significant bits of ADRESH are cleared to 0 0: Left-justified. Six least significant bits of ADRESL are cleared to 0
Bit 6-4: Not used
1: Enable EEPROM write complete interrupt 0: Disable EEPROM write complete interrupt
Bit 3-0: PCFG3-PCFG0 A/D port pin configuration
Figure 3.21 ADCON1 bit definitions
The ADCON1 register configures the functions of the A/D input pins and is used to select the A/D converter reference voltage. The bit definitions of ADCON1 are shown in Figure 3.21. Bit 7 of ADCON1 is called the ADFM bit and controls the format of the converted data. When set to 1, the 10-bit result is right-justified and the six most significant bits of ADRESH are read as 0. When ADFM is cleared to 0, the 10-bit result is left-justified with the six least significant bits of ADRESL read as 0. Bits 0–3 of ADCON1 are used to configure the A/D converter input pins as shown in Figure 3.22.
Note that Vref+ and Vref− in Figure 3.22 are the A/D converter positive and negative reference voltages, respectively. The programmer has the choice of using an external reference voltage, but in most applications Vref+ is programmed to be equal to Vdd (the supply voltage) and Vref− is programmed to be equal to Vss (the supply ground).
The A/D conversion operation must be started by setting the GO/DONE bit of register ADCON0. The end of conversion can be detected in one of two ways. The easiest method is to poll the GO/DONE bit continuously until this bit is cleared. The result is then available in register pair ADRESH:ADRESL. The second method is to program the device to generate interrupts when a conversion is complete.
PCFG3: |
AN7 |
AN6 |
AN5 |
AN4 |
AN3 |
AN2 |
AN1 |
AN0 |
Vref+ |
Vref− |
PCFG0 |
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0000 |
A |
A |
A |
A |
A |
A |
A |
A |
VDD |
VSS |
0001 |
A |
A |
A |
A |
Vref+ |
A |
A |
A |
RA3 |
VSS |
0010 |
D |
D |
D |
A |
A |
A |
A |
A |
VDD |
VSS |
0011 |
D |
D |
D |
A |
Vref+ |
A |
A |
A |
RA3 |
VSS |
0100 |
D |
D |
D |
D |
A |
D |
A |
A |
VDD |
VSS |
0101 |
D |
D |
D |
D |
Vref+ |
D |
A |
A |
RA3 |
VSS |
0110 |
D |
D |
D |
D |
D |
D |
D |
D |
VDD |
VDD |
0111 |
D |
D |
D |
D |
D |
D |
D |
D |
VDD |
VSS |
1000 |
A |
A |
A |
A |
Vref+ |
Vref– |
A |
A |
RA3 |
RA2 |
1001 |
D |
D |
A |
A |
A |
A |
A |
A |
VDD |
VSS |
1010 |
D |
D |
A |
A |
Vref+ |
A |
A |
A |
RA3 |
VSS |
1011 |
D |
D |
A |
A |
Vref+ |
Vref– |
A |
A |
RA3 |
RA2 |
1100 |
D |
D |
D |
A |
Vref+ |
Vref– |
A |
A |
RA3 |
RA2 |
1101 |
D |
D |
D |
D |
Vref+ |
Vref– |
A |
A |
RA3 |
RA2 |
1110 |
D |
D |
D |
D |
D |
D |
D |
A |
VDD |
VSS |
1111 |
D |
D |
D |
D |
Vref+ |
Vref– |
D |
A |
RA3 |
RA2 |
A = analog input D = digital input
Figure 3.22 A/D converter input pin configuration