Файл: Programming Microcontrollers in C, 2-nd edit (Ted Van Sickle, 2001).pdf
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176Chapter 4 Small 8-Bit Systems
0325 26 04 BNE $032B
0327 A6 01 LDA #$01 hrs=1;
0329 B7 C0 STA $C0 }
} |
|||
032B |
20 |
E0 |
BRA $030D } |
032D |
81 |
RTS } |
|
void __TIMER(void) |
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07F8 |
03 |
2E |
{ |
032E |
1D |
08 |
BCLR 6,$08 TCST.RTIF=0; |
0330 |
3C |
C3 |
INC $C3 if (++count==122) |
0332 |
B6 |
C3 |
LDA $C3 |
0334 |
A1 |
7A |
CMP #$7A |
0336 |
26 |
04 |
BNE $033C |
{ |
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Timers |
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0338 |
3C |
C2 |
INC $C2 sec++; |
033A |
3F |
C3 |
CLR $C3 count=0; |
} |
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033C |
80 |
RTI } |
|
07FE 03 |
00 |
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At the beginning of the interrupt service routine there is an entry 07f8, which has a value of 032e, in the address column. This entry places the address of the timer interrupt service routine 0x032e into the timer vector 0x07f8. The code generated in the interrupt service routine is straightforward and little different from what one would expect an assembly language programmer to do. Note, how ever, that the return at the end of the interrupt service routine is an RTI instruction. This is the instruction that causes the microcontroller to restore the processor status to the state that existed when the inter rupt occurred. The normal return from subroutine RTS does not restore the processor state. An RTI must be used to return from interrupt service routines, and any function identified with a vector pragma will be assumed to be an interrupt service routine by the compiler.
It was noted earlier that this timer routine is inaccurate. It is inac curate only because 122 periods of 8.192 milliseconds each total 0.999424 seconds. This seemingly small error will cause big problems
Timers 177
if one wants a real clock because the error amounts to 2.1 seconds per hour. One way this error could be corrected is to adjust the crystal frequency of the microcontroller. Suppose we would use a frequency of 3.996354 MHz instead of 4.0 MHz. This number is derived by
122*2^15/f=1
which yields the above value for f. The 122 periods of 8.196721 milli seconds, which is the real-time interrupt time for this frequency, is exactly 1 second. Another approach involves making small corrections to the time periodically so that on the average the time is correct. An example of an interrupt service routine that makes these corrections is as follows:
void __TIMER(void) /*routine executed every RTI (8.192 ms)*/
{
static int corr1,corr2,corr3;
TCST.RTIF=0; |
/* flags */ |
||||
if (++count==122) |
/* increment seconds */ |
||||
{ |
/* To correct |
for |
8.192 |
*/ |
|
sec++; |
/* ms per |
tick. Run |
122*/ |
||
if(++corr1==14) /* ticks |
per second for */ |
||||
{/* 13 seconds, and 123 */
corr1=0; |
/* for the 14th second */ |
|
if(++corr2==80) /* With this algorithm */ |
||
{ |
/* |
there are 14.000128 */ |
corr2=0; |
/* |
actual seconds per */ |
if(++corr3==4) |
/* 14 indicated. Then */ |
|
{ /* run 79 of |
these */ |
|
count=1; |
/* cycles followed by */ |
|
corr3==0; |
/* one cycle of 14 */ |
|
}/* seconds with 122 ticks */
else /* per second. The */ count=0; /* elapsed time for this*/
}/* cycle is 1120.002048 */
else |
/* seconds |
for |
and */ |
count=(-1); /* |
the |
count is 1120 */ |
|
} /* seconds. Repeat |
this */ |
||
else |
/* cycle 4 times and on */ |
||
178 Chapter 4 Small 8-Bit Systems
count=0; /* the last cycle drop */
}/* one tick makes the */
} |
/* |
indicate and |
elapsed */ |
/* |
time exactly |
4480 sec.*/ |
The three static variables corr1, corr2, and corr3 are used to keep track of the number of times the several different loops in the algorithm are executed. C will always initialize these variables to zero and then their value will be retained from call to call of the function.
16-bit Timers
The multifunction timer discussed in the previous section pro vides for implementation of relatively simple timing functions. Let’s assume that the microcontroller clock frequency is 4.0 MHz. The fastest interrupt time with this system is 0.512 milliseconds, and the granularity of the interrupt times is in large, power-of-two blocks for the RTI system. Also, the relation of the interrupt times to unity is not “clean”; complicated algorithms or special frequency crystals are needed to get the device to respond accurately in seconds.
Often microcontroller applications must provide more than one time function. The 15-bit timer is set up to provide only one time base. Of course, a programmer can program the timer to control many different functions and at many different times. The limits on the functions and times are difficult to determine. It is clear that the fast est practical time base in the 15-bit timer is 0.512 milliseconds. To obtain any finer time resolution, the programmer would have to com pare the TCR bits to a specified value on a cycle-by-cycle basis. This type of program completely consumes the microcontroller and leaves no processing time for other functions during the execution of the timing program. If the time base must be other than some multiple of 0.512 milliseconds and not one of the standard RTI times, the pro cessor can probably service only one time function. If the required times can fall on the above values, the processor can execute several time-based functions limited by the total time required to execute the functions and the microcomputer interrupt latency time.
The 16-bit timer addresses these problems. A block diagram of this type of timer is shown in Figure 4-2. This style of timer contains an internal 16-bit counter that is clocked at some fraction of the
Timers 179
MC68HC05B6 Internal Bus
Internal
Processor
Clock 8-bit
Buffer
High |
Low |
High |
Low |
High |
Low |
High |
Low |
High |
Low |
|||||||
Byte |
Byte |
Byte |
Byte |
Byte |
Byte |
Byte |
Byte |
Byte |
Byte |
|||||||
÷ 4 |
16-bit |
Output |
Output |
Input |
Input |
|||||||||||
Free Running |
$18 |
Compare |
$16 |
Compare |
$1E |
Capture |
$14 |
Capture |
$1C |
|||||||
Counter |
$19 |
Register 1 |
$17 |
Register 2 |
$1F |
Register 1 |
$15 |
Register 2 |
$1D |
|||||||
Counter |
||||||||||||||||
Alternate |
$1A |
|||||||||||||||
Register |
||||||||||||||||
$1B |
||||||||||||||||
Internal Timer Bus
To PLM
Overflow |
Output |
Output |
Edge |
Edge |
||||||
Detect |
Compare |
Compare |
Detect |
Detect |
||||||
Circuit |
Circuit 1 |
Circuit 2 |
Circuit 1 |
Circuit 2 |
||||||
D |
||||||||||||||||||||||||||||||||||||
Q |
||||||||||||||||||||||||||||||||||||
C |
||||||||||||||||||||||||||||||||||||
Latch |
||||||||||||||||||||||||||||||||||||
D |
Q |
|||||||||||||||||||||||||||||||||||
Timer |
7 |
6 |
5 |
4 |
3 |
C |
||||||||||||||||||||||||||||||
Status |
ICF1 |
OCF1 |
TDF |
ICF2 |
OCF2 |
Latch |
||||||||||||||||||||||||||||||
Register |
||||||||||||||||||||||||||||||||||||
$13 |
ICIE |
OCIE |
TOIE |
FOLV2 |
FOLV1 |
OLVL2 |
IEDG1 |
OLVL1 |
Timer |
|||||||||||||||||||||||||||
Control |
||||||||||||||||||||||||||||||||||||
Register |
||||||||||||||||||||||||||||||||||||
$12 |
||||||||||||||||||||||||||||||||||||
TCAP2
Pin
TCAP1
Pin
TCMP2
Pin
TCMP1
Pin
Input Output Overflow Capture Compare Interrupt Interrupt Interrupt $1FF4.5 $1FF8.9 $1FF6.7
Figure 4-2:
16-Bit Timer For The M68HC05B6
180 Chapter 4 Small 8-Bit Systems
microcontroller crystal frequency. An input capture operation de tects the occurrence of an input and transfers the contents of the 16-bit counter into the input capture register. This transfer will al ways set a flag, and it can cause a CPU interrupt if desired. With an input capture system, precise measurement of time interval is pos sible. Details such as phase between two waveforms can be determined or slight differences in frequencies between several signals can be detected. The input capture provides far more accurate time mea surement than can be obtained with either synchronous polling or asynchronous interrupt time measurements. There is a tiny inherent delay between the occurrence of the input and the setting of the input capture register. Such a measurement made by polling an input would require that the computer have a free running counter available to interrogate when the input is detected. Then, the computer would have to be assigned totally to the job of watching the input for the impending transition. When the transition is detected, the value of the counter would have to be read to determine the time of the tran sition. Of course, this sequence of operations would require several computer clock cycles per test, and also several cycles would be re quired to read the counter. Therefore, the accuracy of the time measurement would be compromised by these necessary time delays.
An asynchronous interrupt method to determine the time inter val is better than a polled method, but even this method has built-in errors that make it an impractical means to measure time intervals accurately. The input capture register input system resolves most of the problems associated with accurate measurement of time inter vals with a microcomputer.
Another type of timing problem exists. Suppose that the time that an event is to occur has been calculated. If the time of occur rence is to be accurate, we have a situation like that discussed above. The processor will have to spend all of its time watching the clock to determine when the correct time has arrived. Any time spent on other tasks during this measurement interval will be a latency during which the processor cannot determine if the specified time has arrived. In this case, the accuracy of the event time will be degraded by the time spent on other tasks.
The 16-bit timer avoids this type of problem nicely. An output compare system is used. The time of occurrence is calculated rela
Timers 181
tive to the internal 16-bit counter. This value is placed into an output compare register. The content of the counter is compared automati cally by the microcontroller to the value in the output compare register at each count of the counter. When the two values are equal, a flag is set, an output occurs, and if desired, the CPU is interrupted. The output compare system can be used to generate waveforms, to con trol phases between different waveforms, to control events based on calculated times.
Different microcontrollers will have differing numbers of input capture and output compare registers. In the discussions that follow, details of a single input capture and output compare register will be discussed. It is assumed that these registers are part of an M68HC05B6, so there are two input captures and two output com pares onthe microcontroller. For details on access to the second register set, refer to the appropriate data manual. Later we will see microcontrollers that have many more input capture and output com pare systems (up to 16 on one microcontroller).
Timer Control Register
The timer control register (TCR) is located at the address 0x12. This read/write register controls the operation of the 16-bit timer system. Shown below is a diagram of this register, and a listing of the functions of the various register bits.
TCR |
Bit 7 |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
Bit 0 |
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0x12 |
ICIE |
OCIE |
TOIE |
FOLV1 |
FOLV2 |
CLVL2 |
IEDG1 |
OLVI1 |
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OLVL1 |
Bit 0 Output Level 1. The contents of this bit will be |
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copied to the output level latch the next time an |
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output compare occurs. This result will appear at |
|||||||||||
TCMP1. This bit and the output level latch are |
|||||||||||
cleared when the part is reset. |
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IEDG1 |
Bit 1 Input Edge 1. This bit determines the transition |
||||||||||
direction that will cause an input to occur on In |
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put Capture 1: |
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IEDG1 = 0 Falling Edge |
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IEDG1 = 1 Rising Edge |
|||||||||||
The contents of this bit are undetermined and un affected at reset.
182 Chapter 4 Small 8-Bit Systems
OLVL2 |
Bit 2 Output Level 2. The contents of this bit will be |
copied to the output level latch the next time an |
|
output compare occurs. This result will appear at |
|
TCMP2. This bit and the output level latch are |
|
cleared when the part is reset. |
|
FOLV1 |
Bit 3 Forced Output Compare 1. This bit always reads |
zero. A one written to this position will force the |
|
OLVL1 bit to be copied to the output level latch. |
|
This result will appear at TCMP1. A forced out |
|
put compare does not affect the OCF1 bit in the |
|
timer status register. This bit is cleared at reset. |
|
FOLV2 |
Bit 4 Forced Output Compare 2. This bit always reads |
zero. A one written to this position will force the |
|
OLVL2 bit to be copied to the output level latch. |
|
This result will appear at TCMP2. A forced out |
|
put compare does not affect the OCF2 bit in the |
|
timer status register. This bit is cleared at reset. |
|
TOIE |
Bit 5 Timer Overflow Interrupt Enable. If the TOIE is set, |
the timer overflow interrupt is enabled and an inter |
|
rupt will occur when the TOF flag is set in the timer |
|
status register. This bit is cleared at reset and the in |
|
terrupt is inhibited. |
|
OCIE |
Bit 6 Output Compare Interrupt Enable. If the OCIE bit |
is set, the output compare interrupt is enabled, and |
|
an interrupt will occur whenever either the OCF1 |
|
or the OCF2 is set in the timer status register. This |
|
bit is cleared at reset and the reset is inhibited. |
|
ICIE |
Bit 7 Input Capture Interrupt Enable. If the ICIE bit is |
set, the input compare interrupt is enabled and an |
|
interrupt will occur whenever either the ICF1 or |
|
the ICF2 is set in the timer status register. This |
|
bit is cleared at reset and the reset is inhibited. |
Timer Status Register
This register—TSR—is an 8-bit register. The most significant 5 bits of this register contain read only status information. These bits describe the condition of the 16-bit timer system. Their functions are outlined below: