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Appendix A

14-bit Core Instruction Set

14-bit

16CPX

Dest

CCR

op-code

Instruction

Mnemonic

W F

Z D C

Operation summary

11

1110

LLLL LLLL

ADD Literal to W

addlw LL

√

√

√

√

√

w <- w + #LL

00

0111

dfff ffff

ADD W and F

addwf f,d

√

√

√

√

d <- w + f

11

1110

LLLL LLLL

AND Literal to W

andlw LL

√

√

√

•

•

w <- w · #LL

00

0101

dfff ffff

AND W to F

andwf f,d

√

√

•

•

d <- w · f

01

00nn nfff ffff

Bit Clear File bit n

bcf f,n

√

•

•

•

fn <- 0

01

01nn nfff ffff

Bit Set File bit n

bsf f,n

√

•

•

•

fn <- 1

01

10nn nfff ffff

Bit Test File bit n & Skip if Clear

btfsc f,n

√

•

•

•

pc++ IF fn == 0

01

11nn nfff ffff

Bit Test File bit n & Skip if Set

btfss f,n

√

•

•

•

pc++ IF fn == 1

10

0aaa aaaa aaaa

CALL (jump to) subroutine

call aaa

√

•

•

•

TOS <- pc, pc <- aaa

00

0001

1fff ffff

CLeaR File

clrf f

√

√

•

•

f <- 00

00

0001

0000

0011

CLeaR Working register

clrw

√

•

•

d <- 00

00

0000

0000

0100

CLeaR Watch Dog Timer

clrwdt

•

•

•

wdt <- 00

00

1001

dfff ffff

COMplement File

comf f,d

√

√

√

•

•

d <-

f

00

0011

dfff ffff

DECrement File

decf f,d

√

√

√

•

•

d <- f--

00

1011

dfff ffff

DECrement File & Skip on Zero

decfsz f,d

√

√

•

•

•

d <- f--; pc++ IF == 0

10

1aaa aaaa aaaa

GOTO (jump to) aaa

goto aaa

•

•

•

pc <- aaa

00

1010

dfff ffff

INCrement File

incf f,d

√

√

√

•

•

d <- f++

00

1111

dfff ffff

INCrement File & Skip on Zero

incfsz f,d

√

√

•

•

•

d <- f++; pc++ IF == 0

11

1000

LLLL LLLL

Inclusive OR Literal to W

iorlw LL

√

√

√

•

•

w <- w + #LL

00

0100

dfff ffff

Inclusive OR W to F

iorwf f,d

√

√

•

•

d <- w + f

00

1000

dfff ffff

MOVe in File (load)

movf

f,d

√

√

√

•

•

d <- f

11

0000

LLLL LLLL

MOVe Literal into W

movlw LL

√

•

•

•

w <- #LL

00

0000

1fff ffff

MOVe W out to File (store)

movwf f

√

•

•

•

f <- w

00

0000

0000 0000

No OPeration

nop

•

•

•

Do nothing

11

0100

LLLL LLLL

RETurn from subroutine; L in W

retlw

√

•

•

•

w <- #LL, pc <- TOS

00

0000

0000 1000

RETURN from subroutine

return

•

•

•

pc <- TOS

00

0000

0000 1001

RETurn From IntErrupt

retfie

√

√

•

•

•

GIE <- 1, pc <- TOS

00

1101

dfff ffff

Rotate Left File

rlf f,d

•

•

b7

C

7

file

0

√

√

00

1100

dfff ffff

Rotate Right File

rrf f,d

•

•

b0

7

file

0

C

00

0000

0110 0011

SLEEP mode on

sleep

√

•

•

•

wdt <- 0, Clock off

11

1100

LLLL LLLL

SUB W from Literal

sublw LL

√

√

√

√

w <- #LL - w

00

0010

dfff ffff

SUBtract W from F

subwf f,d

√

√

√

√

d <- w - f

00

1110

dfff ffff

SWAP File nybbles

swapf f,d

√

√

•

•

•

d <- f[7:4] <-> f[3:0]

11

1010

LLLL LLLL

eXclusive OR Literal to W

xorlw LL

√

√

√

•

•

w <- w #LL

00

0110

dfff ffff

eXclusive OR W to F

xorwf f,d

√

√

•

•

d <- w f

√

: Flag operates in the normal manner •

: Not a ected

a…

: Address

d

: Destination; 0 = w, 1 = f

f…

: File register

fn

: File bit n

L…

: Literal data

pc

: Program Counter

w

: Working register

wdt

: Watch Dog Timer/prescaler

TOS : Top Of Stack

== : Equivalent to

pc++ : Jump over next instruction

++

: Add one

-- : Subtract one

GIE : Global Interrupt Enable mask

#

: Constant number

Appendix B

Special Purpose Register Structure for the PIC16C74B

File

Name

7

6

5

4

3

2

1

0

Power-on

All other

Reset

Resets

Bank 0

00h

INDF

Uses contents of this to address Data memory (not a physical register)

01h

TMR0

8-bit real-time clock/counter

XXXX XXXX

UUUU UUUU

02h

PCL1

Lower-order 8 bits of the Program Counter

0000 00000

0000 0000

03h

STATUS1

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1XXX

000? ?UUU

04h

FSR

Indirect Data memory address pointer 0

XXXX XXXX

UUUU UUUU

05h

PORTA

—

—

RA5

RA4

RA3

RA2

RA1

RA0

—-XX XXXX

—-UU UUUU

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

XXXX XXXX

UUUU UUUU

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

XXXX XXXX

UUUU UUUU

08h

PORTD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

XXXX XXXX

UUUU UUUU

09h

PORTE

—

—

—

—

—

RE2

RE1

RE0

—— —XXX

—— —UUU

0Ah

PCLATH

—

—

—

Write bu er for top 5 PC bits

——0 0000

——0 0000

0Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000X

0000 000U

0Ch

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCPIF

TMR2IF

TMR1IF

0000 0000

0000 0000

0Dh

PIR2

—

—

—

—

—

—

—

CCP2IF

—— ——0

—— ——0

0Eh

TMR1L

Timer 1 Low Byte

XXXX XXXX

UUUU UUUU

0Fh

TMR1H

Timer 1 High Byte

XXXX XXXX

UUUU UUUU

10h

T1CON

—

—

T1CKPS1

TICKPS0

T1OSCEN

T1SYNC

TMRCS

TMR1ON

—00 0000

—UU UUUU

11h

TMR2

Timer 2

0000 0000

0000 0000

12h

T2CON

—

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

–000 0000

–000 0000

13h

SSPBUF

Synchronous Serial Port Receive Bu er/ Transmit Register

XXXX XXXX

UUUU UUUU

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1S1

SSPM0

00000 0000

00000 0000

15h

CCPR1L

Capture/Compare/PWM register 1 Low byte

XXXX XXXX

UUUU UUUU

16h

CCPR1H

Capture/Compare/PWM register 1 High byte

XXXX XXXX

UUUU UUUU

17h

CCP1CON

—

—

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

—00 0000

—00 0000

18h

RCSTA

SPEN

RX9

SREN

CREN

—

FERR

OERR

RXD8

0000 –00X

0000 –00X

19h

TXREG

SCI Transmit Data Register

0000 0000

0000 0000

1Ah

RCREG

SCI Receive Data Register

0000 0000

0000 0000

1Bh

CCPR2L

Capture/Compare/PWM register 2 Low byte

XXXX XXXX

UUUU UUUU

1Ch

CCPR2H

Capture/Compare/PWM register 2 High byte

XXXX XXXX

UUUU UUUU

1Dh

CCP2CON

—

—

CCP2X

CCP2Y

CCP2M3

CCP2M2

CCP2M1

CCP2M0

—00 0000

—00 0000

1Eh

ADRES

A/D Result Register

XXXX XXXX

UUUU UUUU

1Fh

ADCON0

ADCS1

ADCS0

CHS2

CHS1

CHS0

GO

—

ADON

0000 00–0

0000 00–0

XNot known

UUnchanged

? Value depends on reset condition.

—Unimplemented; read as 0.

Note 1: Next instruction address if PIC in Sleep mode.

478 The Quintessential PIC Microcontroller

File

Name

7

6

5

4

3

2

1

0

Power-on

All other

address

Reset

Resets

Bank 1

80h

INDF

Uses contents of this to address Data memory (not a physical register)

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

1111 1111

82h

PCL1

Lower-order 8 bits of the Program Counter

0000 00000

0000 0000

83h

STATUS1

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1XXX

000? ?UUU

84h

FSR

Indirect Data memory address pointer 0

XXXX XXXX

UUUU UUUU

85h

TRISA

—

—

Port A Direction Register

—-11 1111

—-11 1111

86h

TRISB

Port B Data Direction Register

1111 1111

1111 1111

87h

TRISC

Port C Data Direction Register

1111 1111

1111 1111

88h

TRISD

Port D Data Direction Register

1111 1111

1111 1111

89h

TRISE

IBF

OBF

IBOV

PSPM

—

TRISE2

TRISE1

TRISE0

0000 –111

0000 –111

8Ah

PCLATH

—

—

—

Write bu er for top 5 PC bits

——0 0000

——0 0000

8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000X

0000 000U

8Ch

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCPIE

TMR2IE

TMR1IE

0000 0000

0000 0000

8Dh

PIE2

—

—

—

—

—

—

—

CCP2IE

—— ——0

—— ——0

8Eh

PCON

—

—

—

—

—

—

—— ——??

—— ——UU

POR

BOR

92h

PR2

Timer 2 Period Register

1111 1111

1111 1111

93h

SSPADD

Synchronous Serial Port (I2C mode) Address Register

0000 0000

0000 0000

94h

SSPSTAT

—

—

D/A

P

S

R/W

UA

BF

—-00 0000

—-00 0000

98h

TXSTA

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 –010

0000 –010

99h

SPBRG

Baud Rate Generator

0000 0000

0000 0000

9Fh

ADCON1

—

—

—

—

—

PCFG2

PCFG1

PCFG0

—— —000

—— —000

XNot known

UUnchanged

? Value depends on reset condition.

—Unimplemented; read as 0.

Note 1: Next instruction address if PIC in Sleep mode.

Appendix C

C Instruction Set

Operator

Operation

Example

Top priority

Direction (associativity)

()

Function call

sqr()

[]

Array element

x[6]

.

Structure element

PIA1.CRA

->

Structure element using a pointer

Unary operators

Direction (associativity)

!

Logical NOT

!x

˜

Inversion (1’s complement)

˜x

-

Negative

y=-x

+

Unary plus

y=x- +(y+z)

++

Increment

x++ or ++x

--

Decrement

x-- or --x

&

Address of

&x

*

Contents of address

*address

(type)

Cast

(long)x

sizeof

Size of object in bytes

sizeof x

Arithmetic

Direction (associativity)

*

Multiplication

z=x*y

/

Division

z=x/y

%

Remainder

z=x%y (Integer types only)

+

Addition

z=x+y

-

Subtraction

z=x-y

Shift

Integer types only

Direction (associativity)

>>

Shift left

z=x>>3

<<

Shift right

z=x<<3

Relational operators

Boolean objects

Direction (associativity)

<

Less than

while (x<3 )

<=

Less than or equal

while (x<=3)

>

Greater than

while (x>3 )

>=

Greater than or equal

while (x>=3)

==

Equivalent

while (x==y)

!=

Not equivalent

while (x!=0)

C operators, their precedence and associativity (continued next page).

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