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480 The Quintessential PIC Microcontroller

Operator	Operation	Example


Bitwise logic		Integer types only

	Direction (associativity)
&	AND	x&0xFE (Clear bit 0)

ˆ	Exclusive-OR	xˆ0x01 (Toggle bit 0)

\|	OR	x\|0x01 (Set bit 0)


Objectwise logic		Boolean objects

	Direction (associativity)
&&	Logical AND	x&&y is True if both x and y are True

\|\|	Logical OR	x\|\|y is True if both or either x and y are True

?:	Conditional	x=(y>z)?5:10 x=5 if y>z True else x=10


Assignment

	Direction (associativity)
=	Simple	x=3
+=	Compound plus	x+=3 e.g. (x=x+3)
-=	Compound minus	x-=3 e.g. (x=x-3)
*=	Compound multiply	x=3 e.g. (x=x3)
/=	Compound divide	x/=3 e.g. (x=x/3)
%=	Compound remainder	x%=3 e.g. (x=x%3)
&=	Compound bit AND	x&=3 e.g. (x=x&3)
ˆ=	Compound bit EX-OR	xˆ=3 e.g. (x=xˆ3)
\|=	Compound bit OR	x\|=3 e.g. (x=x\|3)
<<=	Compound shift left	x<<=3 e.g. (x=x<<3)
>>=	Compound shift right	x>>=3 e.g. (x=x>>3)


	Direction (associativity)
,	Concatenate	if(x=0,y=3;x<10,x++)

Lowest priority

(continued.) C operators, their precedence and associativity.

Appendix D

Acronyms and Abbreviations

ADC (A/D)		Analog to Digital converter/conversion
ADCON0		A/D CONtrol 0; File 08h (PIC16C71)
ADCON1		A/D CONtrol 1; File 88h (PIC16C71)
ADCSn		A/D Clock Select, bits 1:0 in the ADCON0 ﬁle register
ADIE		A/D Interrupt Enable mask; INTCON[6] (PIC16C71X)/PIE1[6]
ADIF		A/D Interrupt Flag; ADCON0[1] (PIC16C71X)/PIR1[6]
ADON		A/D module ON; ADCON0[0]
ADRES		A/D RESult; File 09h/89h (PIC16C71X)/File 1Eh
	ALU	Arithmetic Logic Unit
	ANn	A/D input pin n
	ANSII	American National Standards Institution
	ALU	Arithmetic Logic Unit
	ASCII	American Standard Code for Information Interchange
	BCD	Binary Coded Decimal
	BF	Bu er Full; SSPSTAT[0]
C		Carry ﬂag in the Status register; STATUS[0]
CCP		Capture/Compare PWM module
CCP1		CCP1 input/output pin (Common with RC2)
CCPR1H		CCP Register 1 High byte; File 15h
CCPR1L		CCP Register 1 Low byte; File 16h
	CCP1CON	CCP1 CONtrol register; File 1Dh
	CCP1IE	CCP1 Interrupt Enable mask; PIE1[2]
	CCP1IF	CCP1 Interrupt Flag; PIR1[2]
	CCP2IE	CCP2 Interrupt Enable mask; PIE2[0]
	CCP2IF	CCP2 Interrupt Flag; PIR2[0]
	CCP1M	CCP Mode control; CCP1CON[3:0]
	CHSn	A/D CHannel Select; ADCON[5:3]
	CISC	Complex Instruction Set Computer
	CKP	ClocK Polarity; SSPCON[4]
	CMOS	Complimentary Metal-Oxide Semiconductor
	CREN	Continuous Receive ENable; RCSTA[4]
		Chip Select
	CS
CTS		Clear To Send, RS-232 handshake signal
DAC (D/A)		Digital to Analog converter/conversion
DC		Digit Carry ﬂag in the Status register; STATUS[1]
DC1B		Duty Cycle 1 Bits; CCP1CON[5:4]
DCE		Data Circuit terminating Equipment
DTE		Data Terminal Equipment
ea		E ective Address
EEADR		EEPROM ADdress; File 09h or File 10Dh
EEADRH		EEPROM ADdress High byte; File 10Fh

482 The Quintessential PIC Microcontroller

EECON1	EEPROM CONtrol 1; File 88h or File 18Ch
EECON2	EEPROM CONtrol 2; File 89h or File 18Dh
EEDATA	EEPROM DATA; File 08h or File 10Ch
EEDATH	EEPROM DATa High byte; File 10Eh
EEIE	EEPROM Interrupt Enable mask; INTCON[6] or PIE2[4]
EEIF	EEPROM Interrupt Flag; EECON1[4] or PIR2[4]
EEPGD		EECON1[7].
	EEPROM ProGram/Data;
EEPROM	Electrical Erasable PROM
EPROM	Erasable PROM
FERR	Framing ERRor; RCSTA[2]
FSR	File Select Register; File 4
GIE	Global Interrupt Enable mask; INTCON[7]
	ADC Start Convert (GO)/End Of Conversion (DONE); ADCON0[2]
GO/DONE
GPR	General-Purpose ﬁle Register
GPn	General-purpose Register (I/O port) GPIO pin n
IC	Integrated Circuit
I2C	Inter-Integrated Circuit serial protocol
IDE	Integrated Development Environment
IEC	International Electrotechnical Commission
INDF	INDirect File register; File 0
INT	External INTerrupt input pin (Common with RB0)
INTCON	INTerrupt CONtrol Register; File 0Bh
INTEDG	External INTerrupt EDGe polarity selection; OPTION_REG[0]
INTE	INTerrupt Enable; INTCON[4]
INTF	INTerrupt Flag; INTCON[1]
I/O	Input/Output
IRP	Indirect addressing Register Page; STATUS[7]
ISR	Interrupt Service Routine
LED	Light-Emitting Diode
LSB	Least Signiﬁcant Bit or Byte
LSI	Large Scale Integration
LSD	Least Signiﬁcant Digit
	Master CLeaR reset pin
MCLR
MCU	MicroController Unit
MPU	MicroProcessor Unit
ms	Millisecond (10−3 s)
MSB	Most Signiﬁcant Bit or Byte
MSD	Most Signiﬁcant Digit
MSI	Medium Scale Integration
ns	Nanosecond (10−9 s)
OE	Output Enable
OERR	Overﬂow ERRor; RCSTA[1]
Operating System OS
OPTION_REG	OPTION ﬁle REGister; File 81h
OTP	One-Time Programmable (EPROM)
PC	Program Counter
PC	Personal Computer
PCFGn	A/D Port ConFiGuration; ADCON1[2:0]
PCL	Program Counter Low byte; File 2
PCLATH	Program Counter LATch High byte; File 0Ah
PD	Power Down sleep mode; STATUS[3]
PEIE	PEripheral Interrupt Enable mask; INTCON[6]

		D. Acronyms and Abbreviations 483
PIC		Peripheral Interface Controller
PIPO		Parallel-In Parallel-Out register
PIE1		Peripheral Interrupt Enable register 1, File 8Ch
PIE2		Peripheral Interrupt Enable register 2, File 8Dh
PIR1		Peripheral Interrupt Register 1, File 0Ch
PIR2		Peripheral Interrupt Register 2, File 0Dh
PISO		Parallel-In Serial-Out shift register
PR2		Period Register for Timer 2; File 92h
PRNG		Pseudo Random Number Generator
PROM		Programmable ROM
PS		Post/Prescale rate Select; OPTION_REG[2:0]
PSA		Post/Prescale Scaler Assign; OPTION_REG[3]
PWM		Pulse Width Modulation
RAn		Register (port) A I/O pin n
RAM		Random Access Memory
RBn		Register (port) B I/O pin n
RBIE		Register B Interrupt Enable; INTCON[3]
RBIF		Register B Interrupt Flag; INTCON[0]
		Register B Pull-UP; OPTION_REG[7]
RBPU
RCIE		ReCeive register Interrupt Enable mask; PIE1[5]
RCIF		ReCeive register Interrupt Flag; PIR1[5]
RCREG		ReCeive data REGister; File 1Ah
RCSTA		ReCeive STAtus register; File 18h
RD		ReaD; EECON1[0] ﬁle register
REn		Register (port) E I/O pin n
RISC		Reduced Instruction Set Computer (see CISC)
ROM		Read-Only Memory
RPn		Register Page bits; STATUS[6:5]
rtl		Register Transfer Language
RTS		Ready To Send, RS-232 handshake signal
RX		ReCeive pin for USART (common with RC7)
RX9		ReCeive 9-bit data control; RCSTA[6]
RTCC		Real Time Counter/Clock (see Timer 0)
SAR		Successive Approximation Register
SCK		Serial ClocK in SPI protocol
SDI		Serial Data Input in SPI protocol
SDO		Serial Data Output in SPI protocol
SIPO		Serial-In Parallel-Out shift register
SISO		Serial-In Serial-Out shift register
SP		Stack Pointer
SPBRG		Serial Port Baud-Rate Generator; File 99h
SPEN		Serial Port ENable; RCSTA[7]
SPI		Serial Peripheral Interface protocol
SPR		Special-Purpose ﬁle Register
SSP		Synchronous Serial Port
SSPBUF		SSP BUFfer register; File 13h (PIC16C7X)
SSPCON		SSP CONtrol ﬁle REGister, File 14h
SSPEN		SSP Enable; SSPCON[5]
SSPIE		SSP Interrupt Enable mask; PIE1[3]
SSPIF		SSP Interrupt Flag; PIR1[3]
SSPM		SSP Mode control; SSPCON[3:0]
SSPSR		SSP Shift Register (PIC16C7X)
STATUS		Status Register; File 3

484 The Quintessential PIC Microcontroller

SYNC		SYNChronous mode in the USART; TXSTA[4]
		Watchdog Time Out; STATUS[4]
TO
T0CKI		Timer 0 ClocK Input pin (Common with RA4)
T0CS		Timer 0 Clock Select; OPTION_REG[5]
T0IE		Timer 0 Interrupt Enable mask; INTCON[5]
T0IF		Timer 0 Interrupt Flag; INTCON[2]
T1CKI		Timer 1 ClocK Input pin (Common with RC0)
T1CON		Timer 1 CONtrol register; File 10h
T2CON		Timer 2 CONtrol register; File 12h
	T1OSCEN	Timer 1 OSCillator ENable; T1CON[3]
	T1SYNC	Timer 1 SYNChronize; T1CON[2]
TMR0		TiMeR 0 ﬁle register; File 1
TMR1CS		TiMeR 1 Clock Select; T1CON[1]
TMR1H		TiMeR 1 High byte ﬁle register; File 0Fh
TMR1IE		Timer 1 Interrupt Enable mask; PIE1[0]
	TMR2IE	Timer 2 Interrupt Enable mask; PIE1[1]
	TMR1IF	Timer 1 Interrupt Flag; PIR1[0]
	TMR2IF	Timer 2 Interrupt Flag; PIR1[1]
	TMR1L	TiMeR 1 Low byte ﬁle register; File 0Eh
	TMR1ON	TiMeR 1 ON; T1CON[0]
	TOUTPS	Timer 2 OUTput Post Scaler; T2CON[3:0]
	TRISA	TRIState A (Data Direction register A) File register, File 85h
	TRISB	TRIState B (Data Direction register B) File register, File 86h
	TRISC	TRIState C (Data Direction register C) File register, File 87h
	TRISD	TRIState D (Data Direction register D) File register, File 87h
	T0SE	Timer 0 Set Edge; OPTION_REG[4]
	TTL	Transistor Transistor Logic family
	TTY	TeleTYpewriter
	TX	TranSmit pin for USART (Common with RC6)
	TXEN	TranSmit register ENable; TXSTA[5]
	TXIE	TranSmit register Interrupt Enable mask; PIE1[4]
	TXIF	TranSmit register Interrupt Flag; PIR1[4]
	TXREG	TranSmit data REGister; File 19h
	TXSTA	TranSmit STAtus register; File 98h
	µs	Microsecond (10−6 s)
UART		Universal Asynchronous Receiver Transmitter
USART		Universal Synchronous-Asynchronous Receiver Transmitter
VDD		Positive (Drain) supply voltage
VEE		Earth (0 V) supply voltage
VPP		Positive Programming voltage
VLSI		Very Large-Scale Integration
W		Working register
WCOL		Write COLlision; SSPCON[7]
WR		WRite; EECON1[1]
WREN		WRite ENable; EECON1[2]
WRERR		WRite ERRor; EECON1[3]
Z		Zero ﬂag in the Status register; STATUS[2]

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