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Features

High-performance, Low-power AVR® 8-bit Microcontroller

Advanced RISC Architecture

130 Powerful Instructions – Most Single-clock Cycle Execution

32 x 8 General Purpose Working Registers

Fully Static Operation

Up to 16 MIPS Throughput at 16 MHz

On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation

512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

1K Byte Internal SRAM

Programming Lock for Software Security

Peripheral Features

Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode

One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

Real Time Counter with Separate Oscillator

Three PWM Channels

8-channel ADC in TQFP and MLF package

Eight Channels 10-bit Accuracy

6-channel ADC in PDIP package Eight Channels 10-bit Accuracy

Byte-oriented Two-wire Serial Interface

Programmable Serial USART

Master/Slave SPI Serial Interface

Programmable Watchdog Timer with Separate On-chip Oscillator

On-chip Analog Comparator

Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection

Internal Calibrated RC Oscillator

External and Internal Interrupt Sources

Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby

I/O and Packages

23 Programmable I/O Lines

28-lead PDIP, 32-lead TQFP, and 32-pad MLF

Operating Voltages

2.7 - 5.5V (ATmega8L)

4.5 - 5.5V (ATmega8)

Speed Grades

0 - 8 MHz (ATmega8L)

0 - 16 MHz (ATmega8)

Power Consumption at 4 Mhz, 3V, 25°C

Active: 3.6 mA

Idle Mode: 1.0 mA

Power-down Mode: 0.5 µA

8-bit with 8K Bytes In-System Programmable Flash

ATmega8

ATmega8L

2486O–AVR–10/04


Pin Configurations

PDIP

(RESET) PC6

1

28

PC5 (ADC5/SCL)

(RXD) PD0

2

27

PC4 (ADC4/SDA)

(TXD) PD1

3

26

PC3 (ADC3)

(INT0) PD2

4

25

PC2 (ADC2)

(INT1) PD3

5

24

PC1 (ADC1)

(XCK/T0) PD4

6

23

PC0 (ADC0)

VCC

7

22

GND

GND

8

21

AREF

(XTAL1/TOSC1) PB6

9

20

AVCC

(XTAL2/TOSC2) PB7

10

19

PB5 (SCK)

(T1) PD5

11

18

PB4 (MISO)

(AIN0) PD6

12

17

PB3 (MOSI/OC2)

(AIN1) PD7

13

16

PB2 (SS/OC1B)

(ICP1) PB0

14

15

PB1 (OC1A)

TQFP Top View

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

32

31

30

29

28

27

26

25

(INT1) PD3

1

24

PC1 (ADC1)

(XCK/T0) PD4

2

23

PC0 (ADC0)

GND

3

22

ADC7

VCC

4

21

GND

GND

5

20

AREF

VCC

6

19

ADC6

(XTAL1/TOSC1) PB6

7

18

AVCC

(XTAL2/TOSC2) PB7

8

17

PB5 (SCK)

9

10

11

12

13

14

15

16

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

(INT1) PD3 1 (XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6

(XTAL1/TOSC1) PB6 7 (XTAL2/TOSC2) PB7 8

MLF Top View

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

32

31

30

29

28

27

26

25

9

10

11

12

13

14

15

16

(T1) PD5

(AIN0) PD6

(AIN1) PD7

(ICP1) PB0

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

24 PC1 (ADC1)

23 PC0 (ADC0)

22 ADC7

21 GND

20 AREF

19 ADC6

18 AVCC

17 PB5 (SCK)

NOTE:

The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.

2 ATmega8(L)

2486O–AVR–10/04


ATmega8(L)

Overview

Block Diagram

The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

Figure 1.

Block Diagram

XTAL1

RESET

PC0 - PC6

PB0 - PB7

VCC

XTAL2

PORTC DRIVERS/BUFFERS

PORTB DRIVERS/BUFFERS

GND

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

MUX &

ADC

TWI

ADC

INTERFACE

AGND

AREF

PROGRAM

STACK

TIMERS/

OSCILLATOR

COUNTERS

COUNTER

POINTER

PROGRAM

SRAM

INTERNAL

FLASH

OSCILLATOR

INSTRUCTION

GENERAL

WATCHDOG

OSCILLATOR

REGISTER

PURPOSE

TIMER

REGISTERS

X

INSTRUCTION

Y

MCU CTRL.

DECODER

& TIMING

Z

CONTROL

INTERRUPT

LINES

ALU

UNIT

AVR CPU

STATUS

EEPROM

REGISTER

PROGRAMMING

SPI

USART

LOGIC

+

COMP.

-

INTERFACE

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7

3

2486O–AVR–10/04


The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega8 provides the following features: 8K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23

general purpose I/O lines, 32 general purpose working registers, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial program-

mable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight

channels in TQFP and MLF packages) with 10-bit accuracy, a programmable Watchdog

Timer with Internal Oscillator, an SPI serial port, and five software selectable power sav-

ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,

SPI port, and interrupt system to continue functioning. The Power-down mode saves the

register contents but freezes the Oscillator, disabling all other chip functions until the

next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer contin-

ues to run, allowing the user to maintain a timer base while the rest of the device is

sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except

asynchronous timer and ADC, to minimize switching noise during ADC conversions. In

Standby mode, the crystal/resonator Oscillator is running while the rest of the device is

sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The Flash Program memory can be reprogrammed In-System through an SPI serial

interface, by a conventional non-volatile memory programmer, or by an On-chip boot

program running on the AVR core. The boot program can use any interface to download

the application program in the Application Flash memory. Software in the Boot Flash

Section will continue to run while the Application Flash Section is updated, providing

true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-

Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcon-

troller that provides a highly-flexible and cost-effective solution to many embedded

control applications.

The ATmega8 AVR is supported with a full suite of program and system development

tools, including C compilers, macro assemblers, program debugger/simulators, In-Cir-

cuit Emulators, and evaluation kits.

Disclaimer

Typical values contained in this datasheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

4 ATmega8(L)

2486O–AVR–10/04