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ATmega8(L)

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 28.

Table 28. Port D Pins Alternate Functions

Port Pin

Alternate Function

PD7

AIN1 (Analog Comparator Negative Input)

PD6

AIN0 (Analog Comparator Positive Input)

PD5

T1 (Timer/Counter 1 External Counter Input)

PD4

XCK (USART External Clock Input/Output)

T0 (Timer/Counter 0 External Counter Input)

PD3

INT1 (External Interrupt 1 Input)

PD2

INT0 (External Interrupt 0 Input)

PD1

TXD (USART Output Pin)

PD0

RXD (USART Input Pin)

The alternate pin configuration is as follows:

• AIN1 – Port D, Bit 7

AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.

• AIN0 – Port D, Bit 6

AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.

• T1 – Port D, Bit 5

T1, Timer/Counter1 counter source.

• XCK/T0 – Port D, Bit 4

XCK, USART external clock.

T0, Timer/Counter0 counter source.

• INT1 – Port D, Bit 3

INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.

• INT0 – Port D, Bit 2

INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.

• TXD – Port D, Bit 1

TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1.

• RXD – Port D, Bit 0

RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.

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Table 29 and Table 30 relate the alternate functions of Port D to the overriding signals shown in Figure 25 on page 54.

Table 29. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PD7/AIN1

PD6/AIN0

PD5/T1

PD4/XCK/T0

PUOE

0

0

0

0

PUO

0

0

0

0

OOE

0

0

0

0

OO

0

0

0

0

PVOE

0

0

0

UMSEL

PVO

0

0

0

XCK OUTPUT

DIEOE

0

0

0

0

DIEO

0

0

0

0

DI

T1 INPUT

XCK INPUT / T0 INPUT

AIO

AIN1 INPUT

AIN0 INPUT

Table 30. Overriding Signals for Alternate Functions in PD3..PD0

Signal Name

PD3/INT1

PD2/INT0

PD1/TXD

PD0/RXD

PUOE

0

0

TXEN

RXEN

PUO

0

0

0

PORTD0 •

PUD

OOE

0

0

TXEN

RXEN

OO

0

0

1

0

PVOE

0

0

TXEN

0

PVO

0

0

TXD

0

DIEOE

INT1 ENABLE

INT0 ENABLE

0

0

DIEO

1

1

0

0

DI

INT1 INPUT

INT0 INPUT

RXD

AIO

62 ATmega8(L)

2486O–AVR–10/04


ATmega8(L)

Register Description for I/O Ports

The Port B Data Register –

PORTB

The Port B Data Direction

Register – DDRB

The Port B Input Pins Address

– PINB

The Port C Data Register –

PORTC

The Port C Data Direction

Register – DDRC

The Port C Input Pins Address

– PINC

The Port D Data Register –

PORTD

Bit

7

6

5

4

3

2

1

0

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

PORTB

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

Read/Write

R

R

R

R

R

R

R

R

Initial Value

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Bit

7

6

5

4

3

2

1

0

PORTC6

PORTC5

PORTC4

PORTC3

PORTC2

PORTC1

PORTC0

PORTC

Read/Write

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

DDRC

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

Read/Write

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

PINC

Read/Write

R

R

R

R

R

R

R

R

Initial Value

0

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Bit

7

6

5

4

3

2

1

0

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

The Port D Data Direction

Register – DDRD

The Port D Input Pins Address

– PIND

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

DDRD

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

Read/Write

R

R

R

R

R

R

R

R

Initial Value

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

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