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ATmega8(L)

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 20 summarizes the control signals for the pin value.

Table 20. Port Pin Configurations

PUD

DDxn

PORTxn

(in SFIOR)

I/O

Pull-up

Comment

0

0

X

Input

No

Tri-state (Hi-Z)

0

1

0

Input

Yes

Pxn will source current if external

pulled low.

0

1

1

Input

No

Tri-state (Hi-Z)

1

0

X

Output

No

Output Low (Sink)

1

1

X

Output

No

Output High (Source)

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register Bit. As shown in Figure 22, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure

23 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum propagation delays are denoted tpd,max and

tpd,min, respectively.

Figure 23. Synchronization when Reading an Externally Applied Pin Value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

XXX

in r17, PINx

0x00

0xFF

tpd, max

tpd, min

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2486O–AVR–10/04


Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the suc-

ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1-½ system clock period

depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 24. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

0xFF

out PORTx, r16

nop

in r17, PINx

0x00

0xFF

t pd

52 ATmega8(L)

2486O–AVR–10/04

ATmega8(L)

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

Assembly Code Example(1)

...

;Define pull-ups and set outputs high

;Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins in r16,PINB

...

C Code Example(1)

unsigned char i;

...

/* Define pull-ups and set outputs high */ /* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/

_NOP();

/* Read port pins */ i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable and Sleep As shown in Figure 22, the digital input signal can be clamped to ground at the input of Modes the Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level

close to VCC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 54.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change.

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Unconnected pins

Alternate Port Functions

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.

Most port pins have alternate functions in addition to being general digital I/Os. Figure 25 shows how the port pin control signals from the simplified Figure 22 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 25. Alternate Port Functions(1)

PUOExn

1

PUOVxn

0

PUD

DDOExn

1

DDOVxn

0

Q

D

DDxn

Q CLR

PVOExn

WDx

RESET

PVOVxn

RDx

BUS

Pxn

1

0

Q

D

DATA

PORTxn

DIEOExn

Q CLR

WPx

1

DIEOVxn

RESET

RRx

0

SLEEP

SYNCHRONIZER

RPx

D SET

Q

D

Q

PINxn

L CLR

Q

CLR Q

clk I/O

DIxn

AIOxn

PUOExn:

Pxn PULL-UP OVERRIDE ENABLE

PUD:

PULLUP DISABLE

PUOVxn:

Pxn PULL-UP OVERRIDE VALUE

WDx:

WRITE DDRx

DDOExn:

Pxn DATA DIRECTION OVERRIDE ENABLE

RDx:

READ DDRx

DDOVxn:

Pxn DATA DIRECTION OVERRIDE VALUE

RRx:

READ PORTx REGISTER

PVOExn:

Pxn PORT VALUE OVERRIDE ENABLE

WPx:

WRITE PORTx

PVOVxn:

Pxn PORT VALUE OVERRIDE VALUE

RPx:

READ PORTx PIN

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

clk :

I/O CLOCK

DIEOVxn:

Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

I/O

DIGITAL INPUT PIN n ON PORTx

DIxn:

SLEEP:

SLEEP CONTROL

AIOxn:

ANALOG INPUT/OUTPUT PIN n ON PORTx

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

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ATmega8(L)

Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.

Table 21. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

PUOE

Pull-up Override

If this signal is set, the pull-up enable is controlled by

Enable

the PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV

Pull-up Override

If PUOE is set, the pull-up is enabled/disabled when

Value

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

DDOE

Data Direction

If this signal is set, the Output Driver Enable is

Override Enable

controlled by the DDOV signal. If this signal is cleared,

the Output driver is enabled by the DDxn Register bit.

DDOV

Data Direction

If DDOE is set, the Output Driver is enabled/disabled

Override Value

when DDOV is set/cleared, regardless of the setting of

the DDxn Register bit.

PVOE

Port Value

If this signal is set and the Output Driver is enabled,

Override Enable

the port value is controlled by the PVOV signal. If

PVOE is cleared, and the Output Driver is enabled, the

port Value is controlled by the PORTxn Register bit.

PVOV

Port Value

If PVOE is set, the port value is set to PVOV,

Override Value

regardless of the setting of the PORTxn Register bit.

DIEOE

Digital Input Enable

If this bit is set, the Digital Input Enable is controlled by

Override Enable

the DIEOV signal. If this signal is cleared, the Digital

Input Enable is determined by MCU-state (Normal

mode, sleep modes).

DIEOV

Digital Input Enable

If DIEOE is set, the Digital Input is enabled/disabled

Override Value

when DIEOV is set/cleared, regardless of the MCU

state (Normal mode, sleep modes).

DI

Digital Input

This is the Digital Input to alternate functions. In the

figure, the signal is connected to the output of the

schmitt trigger but before the synchronizer. Unless the

Digital Input is used as a clock source, the module with

the alternate function will use its own synchronizer.

AIO

Analog Input/output

This is the Analog Input/output to/from alternate

functions. The signal is connected directly to the pad,

and can be used bi-directionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

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