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update of the OCR1x Compare Register to either TOP or BOTTOM of the counting

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical

PWM pulses, thereby making the output glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double

buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x

(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter

does not update this register automatically as the TCNT1 and ICR1 Register). Therefore

OCR1x is not read via the High byte temporary register (TEMP). However, it is a good

practice to read the Low byte first as when accessing other 16-bit registers. Writing the

OCR1x Registers must be done via the TEMP Register since the compare of all 16-bit is

done continuously. The High byte (OCR1xH) has to be written first. When the High byte

I/O location is written by the CPU, the TEMP Register will be updated by the value writ-

ten. Then when the Low byte (OCR1xL) is written to the lower eight bits, the High byte

will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Reg-

ister in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 77.

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare

Match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be

updated as if a real Compare Match had occurred (the COM1x1:0 bits settings define

whether the OC1x pin is set, cleared or toggled).

Compare Match Blocking by

All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the

TCNT1 Write

next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be

initialized to the same value as TCNT1 without triggering an interrupt when the

Timer/Counter clock is enabled.

Using the Output Compare

Since writing TCNT1 in any mode of operation will block all compare matches for one

Unit

timer clock cycle, there are risks involved when changing TCNT1 when using any of the

Output Compare channels, independent of whether the Timer/Counter is running or not.

If the value written to TCNT1 equals the OCR1x value, the Compare Match will be

missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to

TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be

ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value

equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC1x value is to use the Force

Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its

value even when changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare

value. Changing the COM1x1:0 bits will take effect immediately.

Compare Output Mode and

The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM

Waveform Generation

modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no

action on the OC1x Register is to be performed on the next Compare Match. For com-

pare output actions in the non-PWM modes refer to Table 36 on page 95. For fast PWM

mode refer to Table 37 on page 96, and for phase correct and phase and frequency cor-

rect PWM refer to Table 38 on page 96.

A change of the COM1x1:0 bits state will have effect at the first Compare Match after

the bits are written. For non-PWM modes, the action can be forced to have immediate

effect by using the FOC1x strobe bits.

Modes of Operation

The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare

pins) is defined by the combination of the Waveform Generation mode (WGM13:0) and

Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0

bits control whether the PWM output generated should be inverted or not (inverted or

non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the out-

put should be set, cleared or toggle at a Compare Match. See “Compare Match Output

Unit” on page 85.

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 93.

Normal Mode

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the

counting direction is always up (incrementing), and no counter clear is performed. The

counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and

then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-

flow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.

The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV1

Flag, the timer resolution can be increased by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-

mum interval between the external events must not exceed the resolution of the counter.

If the interval between events are too long, the timer overflow interrupt or the prescaler

must be used to extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

Clear Timer on Compare

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1

Match (CTC) Mode

Register are used to manipulate the counter resolution. In CTC mode the counter is

cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0

= 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the

counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 37. The counter value

(TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then

counter (TCNT1) is cleared.