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ATmega8(L)
Timer/Counter Timing
Diagrams
to 3. See Table 38 on page 96. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation:
fOCnxPFCPWM = |
fclk_I/O |
2--------N---------TOP---------- |
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 41 shows a timing diagram for the setting of OCF1x.
Figure 41. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn |
OCRnx - 1 |
OCRnx |
OCRnx + 1 |
OCRnx + 2 |
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OCRnx |
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OCRnx Value |
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OCFnx
Figure 42 shows the same timing data, but with the prescaler enabled.
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2486O–AVR–10/04
Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
clkI/O |
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clkTn |
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(clkI/O/8) |
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TCNTn |
OCRnx - 1 |
OCRnx |
OCRnx + 1 |
OCRnx + 2 |
OCRnx |
OCRnx Value |
OCFnx
Figure 43 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM.
Figure 43. Timer/Counter Timing Diagram, no Prescaling
clkI/O |
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clkTn |
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(clkI/O/1) |
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TCNTn |
TOP - 1 |
TOP |
BOTTOM |
BOTTOM + 1 |
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(CTC and FPWM) |
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TCNTn |
TOP - 1 |
TOP |
TOP - 1 |
TOP - 2 |
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(PC and PFC PWM) |
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TOVn (FPWM) |
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and ICFn (if used |
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as TOP) |
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OCRnx |
Old OCRnx Value |
New OCRnx Value |
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(Update at TOP) |
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Figure 44 shows the same timing data, but with the prescaler enabled.
94 ATmega8(L)
2486O–AVR–10/04
16-bit Timer/Counter
Register Description
Timer/Counter 1 Control
Register A – TCCR1A
2486O–AVR–10/04
ATmega8(L)
Figure 44. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O |
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clkTn |
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(clkI/O/8) |
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TCNTn |
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TOP - 1 |
TOP |
BOTTOM |
BOTTOM + 1 |
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(CTC and FPWM) |
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TCNTn |
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TOP - 1 |
TOP |
TOP - 1 |
TOP - 2 |
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(PC and PFC PWM) |
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TOVn (FPWM) |
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and ICFn (if used |
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as TOP) |
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OCRnx |
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Old OCRnx Value |
New OCRnx Value |
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(Update at TOP) |
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Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
COM1A1 |
COM1A0 |
COM1B1 |
COM1B0 |
FOC1A |
FOC1B |
WGM11 |
WGM10 |
TCCR1A |
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
W |
W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
•Bit 7:6 – COM1A1:0: Compare Output Mode for channel A
•Bit 5:4 – COM1B1:0: Compare Output Mode for channel B
The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 36 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM).
Table 36. Compare Output Mode, Non-PWM
COM1A1/ |
COM1A0/ |
|
COM1B1 |
COM1B0 |
Description |
0 |
0 |
Normal port operation, OC1A/OC1B disconnected. |
0 |
1 |
Toggle OC1A/OC1B on Compare Match |
1 |
0 |
Clear OC1A/OC1B on Compare Match (Set output to low level) |
1 |
1 |
Set OC1A/OC1B on Compare Match (Set output to high level) |
95
Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Table 37. Compare Output Mode, Fast PWM(1)
COM1A1/ |
COM1A0/ |
|
COM1B1 |
COM1B0 |
Description |
0 |
0 |
Normal port operation, OC1A/OC1B disconnected. |
0 |
1 |
WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B |
disconnected (normal port operation). For all other WGM1 |
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settings, normal port operation, OC1A/OC1B disconnected. |
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1 |
0 |
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP |
1 |
1 |
Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP |
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 87. for more details.
Table 38 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode.
Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
COM1A1/ |
COM1A0/ |
|
COM1B1 |
COM1B0 |
Description |
0 |
0 |
Normal port operation, OC1A/OC1B disconnected. |
0 |
1 |
WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B |
disconnected (normal port operation). For all other WGM1 |
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settings, normal port operation, OC1A/OC1B disconnected. |
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1 |
0 |
Clear OC1A/OC1B on Compare Match when up-counting. Set |
OC1A/OC1B on Compare Match when downcounting. |
11 Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 89. for more details.
•Bit 3 – FOC1A: Force Output Compare for channel A
•Bit 2 – FOC1B: Force Output Compare for channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and
96 ATmega8(L)
2486O–AVR–10/04
ATmega8(L)
what type of waveform generation to be used, see Table 39. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 86.)
Table 39. Waveform Generation Mode Bit Description
WGM12 |
WGM11 |
WGM10 |
Timer/Counter Mode of |
Update of |
TOV1 Flag |
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Mode |
WGM13 |
(CTC1) |
(PWM11) |
(PWM10) |
Operation(1) |
TOP |
OCR1x |
Set on |
0 |
0 |
0 |
0 |
0 |
Normal |
0xFFFF |
Immediate |
MAX |
1 |
0 |
0 |
0 |
1 |
PWM, Phase Correct, 8-bit |
0x00FF |
TOP |
BOTTOM |
2 |
0 |
0 |
1 |
0 |
PWM, Phase Correct, 9-bit |
0x01FF |
TOP |
BOTTOM |
3 |
0 |
0 |
1 |
1 |
PWM, Phase Correct, 10-bit |
0x03FF |
TOP |
BOTTOM |
4 |
0 |
1 |
0 |
0 |
CTC |
OCR1A |
Immediate |
MAX |
5 |
0 |
1 |
0 |
1 |
Fast PWM, 8-bit |
0x00FF |
TOP |
TOP |
6 |
0 |
1 |
1 |
0 |
Fast PWM, 9-bit |
0x01FF |
TOP |
TOP |
7 |
0 |
1 |
1 |
1 |
Fast PWM, 10-bit |
0x03FF |
TOP |
TOP |
8 |
1 |
0 |
0 |
0 |
PWM, Phase and Frequency Correct |
ICR1 |
BOTTOM |
BOTTOM |
9 |
1 |
0 |
0 |
1 |
PWM, Phase and Frequency Correct |
OCR1A |
BOTTOM |
BOTTOM |
10 |
1 |
0 |
1 |
0 |
PWM, Phase Correct |
ICR1 |
TOP |
BOTTOM |
11 |
1 |
0 |
1 |
1 |
PWM, Phase Correct |
OCR1A |
TOP |
BOTTOM |
12 |
1 |
1 |
0 |
0 |
CTC |
ICR1 |
Immediate |
MAX |
13 |
1 |
1 |
0 |
1 |
(Reserved) |
– |
– |
– |
14 |
1 |
1 |
1 |
0 |
Fast PWM |
ICR1 |
TOP |
TOP |
15 |
1 |
1 |
1 |
1 |
Fast PWM |
OCR1A |
TOP |
TOP |
Note: |
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and |
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location of these bits are compatible with previous versions of the timer.
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2486O–AVR–10/04