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ATmega8(L)

Figure 81. Formats and States in the Master Receiver Mode

MR

Successfull

S

SLA

R

A

DATA

A

DATA

P

reception

A

from a slave

receiver

$08

$40

$50

$58

Next transfer

RS

SLA

R

started with a

repeated start

condition

$10

Not acknowledge

W

P

received after the

A

slave address

$48

Arbitration lost in slave

MT

Other master

Other master

address or data byte

A or A

continues

A

continues

$38

$38

Arbitration lost and

A

Other master

addressed as slave

continues

To corresponding

$68

$78 $B0

states in slave mode

Any number of data bytes

From master to slave

DATA

A

and their associated acknowledge bits

From slave to master

n

This number (contained in TWSR) corresponds

to a defined state of the Two-Wire Serial Bus. The

prescaler bits are zero or masked to zero

Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a Master Trans-

mitter (see Figure 82). All the status codes mentioned in this section assume that the

prescaler bits are zero or are masked to zero.

Figure 82. Data transfer in Slave Receiver mode

VCC

Device 1

Device 2

Device 3

........

Device n

R1

R2

SLAVE

MASTER

RECEIVER

TRANSMITTER

SDA

SCL

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

181

2486O–AVR–10/04

The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

0

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 68. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes.

182 ATmega8(L)

2486O–AVR–10/04

ATmega8(L)

Table 68. Status Codes for Slave Receiver Mode

Status Code

Application Software Response

(TWSR)

Status of the Two-wire Serial Bus

To TWCR

Prescaler Bits

and Two-wire Serial

Interface

To/from TWDR

are 0

Hardware

STA

STO

TWINT

TWEA

Next Action Taken by TWI Hardware

0x60

Own SLA+W has been received;

No TWDR action or

X

0

1

0

Data byte will be received and NOT ACK will be

ACK has been returned

No TWDR action

X

0

1

1

returned

Data byte will be received and ACK will be returned

0x68

Arbitration lost in SLA+R/W as

No TWDR action or

X

0

1

0

Data byte will be received and NOT ACK will be

Master; own SLA+W has been

returned

received; ACK has been returned

No TWDR action

X

0

1

1

Data byte will be received and ACK will be returned

0x70

General call address has been

No TWDR action or

X

0

1

0

Data byte will be received and NOT ACK will be

received; ACK has been returned

No TWDR action

X

0

1

1

returned

Data byte will be received and ACK will be returned

0x78

Arbitration lost in SLA+R/W as

No TWDR action or

X

0

1

0

Data byte will be received and NOT ACK will be

Master; General call address has

No TWDR action

X

0

1

1

returned

been received; ACK has been

Data byte will be received and ACK will be returned

returned

0x80

Previously addressed

with own

Read data byte or

X

0

1

0

Data byte will be received and NOT ACK will be

SLA+W; data has been received;

returned

ACK has been returned

Read data byte

X

0

1

1

Data byte will be received and ACK will be returned

0x88

Previously addressed

with own

Read data byte or

0

0

1

0

Switched to the not addressed Slave mode;

SLA+W; data has been received;

0

1

1

no recognition of own SLA or GCA

NOT ACK has been returned

Read data byte or

0

Switched to the not addressed Slave mode;

own SLA will be recognized;

0

1

0

GCA will be recognized if TWGCE = “1”

Read data byte or

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

0

1

1

becomes free

Read data byte

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0x90

Previously addressed with

Read data byte or

X

0

1

0

Data byte will be received and NOT ACK will be

general call; data has been re-

returned

ceived; ACK has been returned

Read data byte

X

0

1

1

Data byte will be received and ACK will be returned

0x98

Previously addressed with

Read data byte or

0

0

1

0

Switched to the not addressed Slave mode;

general call; data has been

no recognition of own SLA or GCA

received; NOT ACK has been

Read data byte or

0

0

1

1

Switched to the not addressed Slave mode;

returned

own SLA will be recognized;

Read data byte or

1

0

1

0

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

Read data byte

1

0

1

1

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xA0

A STOP condition or repeated

No action

0

0

1

0

Switched to the not addressed Slave mode;

START condition has been

no recognition of own SLA or GCA

received while still addressed as

0

0

1

1

Switched to the not addressed Slave mode;

Slave

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

1

0

1

0

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

1

0

1

1

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

183

2486O–AVR–10/04

Figure 83. Formats and States in the Slave Receiver Mode

Reception of the own

S

SLA

W

A

DATA

A

DATA

A

P or S

slave address and one or

more data bytes. All are

acknowledged

$60

$80

$80

$A0

Last data byte received

P or S

is not acknowledged

A

$88

Arbitration lost as master

A

and addressed as slave

$68

Reception of the general call

General Call

A

DATA

A

DATA

A

P or S

address and one or more data

bytes

$70

$90

$90

$A0

Last data byte received is

P or S

not acknowledged

A

$98

Arbitration lost as master and

A

addressed as slave by general call

$78

Any number of data bytes

From master to slave

DATA

A

and their associated acknowledge bits

From slave to master

n

This number (contained in TWSR) corresponds

to a defined state of the Two-Wire Serial Bus. The

prescaler bits are zero or masked to zero

184 ATmega8(L)

2486O–AVR–10/04

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