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ATmega8(L)
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
1 |
X |
1 |
0 |
X |
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus..
Table 66. Status codes for Master Transmitter Mode
Status Code |
Application Software Response |
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(TWSR) |
Status of the Two-wire Serial |
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To/from TWDR |
To TWCR |
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Prescaler Bits |
Bus and Two-wire Serial Inter- |
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are 0 |
face Hardware |
STA |
STO |
TWINT |
TWEA |
Next Action Taken by TWI Hardware |
|
0x08 |
A START condition has been |
Load SLA+W |
0 |
0 |
1 |
X |
SLA+W will be transmitted; |
transmitted |
ACK or NOT ACK will be received |
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0x10 |
A repeated START condition |
Load SLA+W or |
0 |
0 |
1 |
X |
SLA+W will be transmitted; |
has been transmitted |
ACK or NOT ACK will be received |
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Load SLA+R |
0 |
0 |
1 |
X |
SLA+R will be transmitted; |
||
Logic will switch to Master Receiver mode |
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0x18 |
SLA+W has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
ACK has been received |
No TWDR action or |
1 |
0 |
1 |
X |
be received |
|
Repeated START will be transmitted |
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No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
||
No TWDR action |
1 |
1 |
1 |
X |
TWSTO Flag will be reset |
||
STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
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0x20 |
SLA+W has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
NOT ACK has been received |
No TWDR action or |
1 |
0 |
1 |
X |
be received |
|
Repeated START will be transmitted |
|||||||
No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
||
No TWDR action |
1 |
1 |
1 |
X |
TWSTO Flag will be reset |
||
STOP condition followed by a START condition will be |
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transmitted and TWSTO Flag will be reset |
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0x28 |
Data byte has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
ACK has been received |
X |
be received |
|||||
No TWDR action or |
1 |
0 |
1 |
Repeated START will be transmitted |
|||
No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
||
1 |
X |
TWSTO Flag will be reset |
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No TWDR action |
1 |
1 |
STOP condition followed by a START condition will be |
||||
transmitted and TWSTO Flag will be reset |
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0x30 |
Data byte has been transmitted; |
Load data byte or |
0 |
0 |
1 |
X |
Data byte will be transmitted and ACK or NOT ACK will |
NOT ACK has been received |
No TWDR action or |
1 |
0 |
1 |
X |
be received |
|
Repeated START will be transmitted |
|||||||
No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and |
||
No TWDR action |
1 |
1 |
1 |
X |
TWSTO Flag will be reset |
||
STOP condition followed by a START condition will be |
|||||||
transmitted and TWSTO Flag will be reset |
|||||||
0x38 |
Arbitration lost in SLA+W or data |
No TWDR action or |
0 |
0 |
1 |
X |
Two-wire Serial Bus will be released and not addressed |
bytes |
No TWDR action |
1 |
0 |
1 |
X |
Slave mode entered |
|
A START condition will be transmitted when the bus be- |
|||||||
comes free |
|||||||
177
2486O–AVR–10/04
Figure 79. Formats and States in the Master Transmitter Mode
MT
Successfull |
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S |
SLA |
W |
A |
DATA |
A |
P |
||||||||||||
transmission |
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to a slave |
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receiver |
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$08 |
$18 |
$28 |
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Next transfer |
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RS |
SLA |
W |
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started with a |
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repeated start |
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condition |
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$10 |
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Not acknowledge |
R |
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P |
||||||||||||||||||
received after the |
A |
|||||||||||||||||
slave address |
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$20
MR
Not acknowledge
received after a data A P byte
$30 |
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Arbitration lost in slave |
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Other master |
Other master |
||||||||||||||
address or data byte |
A or A |
continues |
A or A |
continues |
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$38 |
$38 |
||||||||||||||
Arbitration lost and |
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A |
Other master |
||||||||||||||
addressed as slave |
continues |
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To corresponding |
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$68 |
$78 |
$B0 |
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states in slave mode |
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From master to slave |
DATA |
A |
Any number of data bytes |
|
and their associated acknowledge bits |
||||
From slave to master |
n |
This number (contained in TWSR) corresponds |
||
to a defined state of the Two-Wire Serial Bus. The |
||||
prescaler bits are zero or masked to zero
178 ATmega8(L)
2486O–AVR–10/04
ATmega8(L) |
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Master Receiver Mode |
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In the Master Receiver mode, a number of data bytes are received from a Slave Trans- |
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mitter (see Figure 80). In order to enter a Master mode, a START condition must be |
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transmitted. The format of the following address packet determines whether Master |
|||
Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT |
|||
mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes |
|||
mentioned in this section assume that the prescaler bits are zero or are masked to zero. |
|||
Figure 80. Data Transfer in Master Receiver Mode |
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VCC |
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Device 1 |
Device 2 |
Device 3 |
........ |
||||||||||||
Device n |
R1 |
R2 |
|||||||||||||
MASTER |
SLAVE |
||||||||||||||
RECEIVER |
TRANSMITTER |
||||||||||||||
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (See Table 66). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
0 |
X |
1 |
0 |
X |
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in Table 67. Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
0 |
1 |
X |
1 |
0 |
X |
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR |
TWINT |
TWEA |
TWSTA |
TWSTO |
TWWC |
TWEN |
– |
TWIE |
value |
1 |
X |
1 |
0 |
X |
1 |
0 |
X |
179
2486O–AVR–10/04
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access |
|||||||||||
the same Slave again, or a new Slave without transmitting a STOP condition. Repeated |
|||||||||||
START enables the Master to switch between Slaves, Master Transmitter mode and |
|||||||||||
Master Receiver mode without losing control over the bus. |
|||||||||||
Table 67. Status codes for Master Receiver Mode |
|||||||||||
Status Code |
Application Software Response |
||||||||||
(TWSR) |
Status of the Two-wire Serial |
To TWCR |
|||||||||
Prescaler Bits |
Bus and Two-wire Serial Inter- |
To/from TWDR |
|||||||||
are 0 |
face Hardware |
STA |
STO |
TWINT |
TWEA |
Next Action Taken by TWI Hardware |
|||||
0x08 |
A START condition has been |
Load SLA+R |
0 |
0 |
1 |
X |
SLA+R will be transmitted |
||||
transmitted |
ACK or NOT ACK will be received |
||||||||||
0x10 |
A repeated START condition |
Load SLA+R or |
0 |
0 |
1 |
X |
SLA+R will be transmitted |
||||
has been transmitted |
Load SLA+W |
0 |
0 |
1 |
X |
ACK or NOT ACK will be received |
|||||
SLA+W will be transmitted |
|||||||||||
Logic will switch to Master Transmitter mode |
|||||||||||
0x38 |
Arbitration lost in SLA+R or NOT |
No TWDR action or |
0 |
0 |
1 |
X |
Two-wire Serial Bus will be released and not addressed |
||||
ACK bit |
No TWDR action |
1 |
0 |
1 |
X |
Slave mode will be entered |
|||||
A START condition will be transmitted when the bus |
|||||||||||
becomes free |
|||||||||||
0x40 |
SLA+R has been transmitted; |
No TWDR action or |
0 |
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
||||
ACK has been received |
No TWDR action |
0 |
0 |
1 |
1 |
returned |
|||||
Data byte will be received and ACK will be returned |
|||||||||||
0x48 |
SLA+R has been transmitted; |
No TWDR action or |
1 |
0 |
1 |
X |
Repeated START will be transmitted |
||||
NOT ACK has been received |
No TWDR action or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and TWSTO Flag will |
|||||
No TWDR action |
1 |
1 |
1 |
X |
be reset |
||||||
STOP condition followed by a START condition will be |
|||||||||||
transmitted and TWSTO Flag will be reset |
|||||||||||
0x50 |
Data byte has been received; |
Read data byte or |
0 |
0 |
1 |
0 |
Data byte will be received and NOT ACK will be |
||||
ACK has been returned |
Read data byte |
0 |
0 |
1 |
1 |
returned |
|||||
Data byte will be received and ACK will be returned |
|||||||||||
0x58 |
Data byte has been received; |
Read data byte or |
1 |
0 |
1 |
X |
Repeated START will be transmitted |
||||
NOT ACK has been returned |
Read data byte or |
0 |
1 |
1 |
X |
STOP condition will be transmitted and TWSTO Flag will |
|||||
1 |
1 |
1 |
X |
be reset |
|||||||
Read data byte |
STOP condition followed by a START condition will be |
||||||||||
transmitted and TWSTO Flag will be reset |
|||||||||||
180 ATmega8(L)
2486O–AVR–10/04