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External Reset |
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An External Reset is generated by a low level on the RESET pin. Reset pulses longer |
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than the minimum pulse width (see Table 15) will generate a reset, even if the clock is |
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not running. Shorter pulses are not guaranteed to generate a reset. When the applied |
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signal reaches the Reset Threshold Voltage – VRST on its positive edge, the delay |
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counter starts the MCU after the time-out period tTOUT has expired. |
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Figure 17. External Reset During Operation |
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CC |
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Brown-out Detection |
ATmega8 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC |
level during operation by comparing it to a fixed trigger level. The trigger level for the |
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BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), |
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or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike |
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free Brown-out Detection. The hysteresis on the detection level should be interpreted as |
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VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. |
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The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is |
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enabled (BODEN programmed), and VCC decreases to a value below the trigger level |
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(VBOT- in Figure 18), the Brown-out Reset is immediately activated. When VCC increases |
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above the trigger level (VBOT+ in Figure 18), the delay counter starts the MCU after the |
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time-out period tTOUT has expired. |
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The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level |
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for longer than tBOD given in Table 15. |
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Figure 18. Brown-out Reset During Operation |
VCC |
VBOT+ |
VBOT- |
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RESET |
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TIME-OUT |
tTOUT |
INTERNAL |
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RESET |
38 ATmega8(L)
2486O–AVR–10/04
ATmega8(L) |
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Watchdog Reset |
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When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura- |
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tion. On the falling edge of this pulse, the delay timer starts counting the time-out period |
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tTOUT. Refer to page 41 for details on operation of the Watchdog Timer. |
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Figure 19. Watchdog Reset During Operation |
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CC |
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CK
MCU Control and Status |
The MCU Control and Status Register provides information on which reset source |
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Register – MCUCSR |
caused an MCU Reset. |
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Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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MCUCSR |
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– |
– |
– |
– |
WDRF |
BORF |
EXTRF |
PORF |
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Read/Write |
R |
R |
R |
R |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
0 |
See Bit Description |
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• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
39
2486O–AVR–10/04
Internal Voltage |
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ATmega8 features an internal bandgap reference. This reference is used for Brown-out |
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Reference |
Detection, and it can be used as an input to the Analog Comparator or the ADC. The |
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2.56V reference to the ADC is generated from the internal bandgap reference. |
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Voltage Reference Enable The voltage reference has a start-up time that may influence the way it should be used. Signals and Start-up Time The start-up time is given in Table 16. To save power, the reference is not always turned on. The reference is on during the following situations:
1.When the BOD is enabled (by programming the BODEN Fuse).
2.When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3.When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.
Table 16. Internal Voltage Reference Characteristics
Symbol |
Parameter |
Min |
Typ |
Max |
Units |
VBG |
Bandgap reference voltage |
1.15 |
1.23 |
1.40 |
V |
tBG |
Bandgap reference start-up time |
40 |
70 |
µs |
|
IBG |
Bandgap reference current consumption |
10 |
µA |
40 ATmega8(L)
2486O–AVR–10/04
ATmega8(L)
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 17 on page 42. The WDR – Watchdog Reset
– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega8 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to page 39.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 20. Watchdog Timer
WATCHDOG
OSCILLATOR
Watchdog Timer Control
Register – WDTCR
2486O–AVR–10/04
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
– |
– |
– |
WDCE |
WDE |
WDP2 |
WDP1 |
WDP0 |
WDTCR |
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Read/Write |
R |
R |
R |
R/W |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See the Code Examples on page 43.
41