Файл: ATmega8.pdf

Timed Sequences for Changing the Configuration of the Watchdog Timer

Safety Level 1 (WDTON Fuse

Unprogrammed)

Safety Level 2 (WDTON Fuse

Programmed)

2486O–AVR–10/04

ATmega8(L)

The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate procedures are described for each level.

Assembly Code Example

WDT_off:

; reset WDT

WDR

; Write logical one to WDCE and WDE in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16

; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret

C Code Example

void WDT_off(void)

{

/* reset WDT */ _WDR();

/* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */ WDTCR = 0x00;

}

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer and/or changing the Watchdog Time-out, the following procedure must be followed:

1.In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2.Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed:

1.In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

43

Interrupts

Interrupt Vectors in

ATmega8

This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12.

Table 18. Reset and Interrupt Vectors

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 206.

2.When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the boot Flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the boot Flash section.

Table 19 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa.