Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

Devices from earlier CMOS families are designated by a part number of the form 4NNNB or 4NNNUB.

5.Devices of the same logic family generally have the same electrical characteristics.

6.Data such as input/output voltages and currents are specified in manufacturers’ datasheets. Only the maximum or minimum values of these parameters should be used as design information. “Typical” values should be regarded as “information only.”

7.The time required for an a logic circuit output to change as a result of an input change is called propagation delay.

8.Propagation delay is specified as tpLH when an output changes from LOW to HIGH and tpHL when the output goes from HIGH to LOW.

9.Propagation delay in a circuit is the sum of all delays in the slowest input-to-output path. Gates whose outputs do not change are ignored in the calculation.

10.Fanout is the maximum number of device inputs that can be driven by the output of a logic device.

11.The actual value of output current in a driving gate is the sum of all load currents, which are the input currents of the load gates. For n loads,

IOL IIL1 IIL2 … IILnL nL IIL

and IOH IIH1 IIH2 … IIHnH nHIIH

12.The fanout of the driving gate in the LOW and HIGH states can be calculated as:

IOL nL IIL

IOH

and nH I

IH

which are HIGH and nL of which are LOW.

16.CMOS devices draw most current from the power supply when its outputs are switching and very little when they are static. Power dissipation of a high-speed CMOS device with n outputs has a static and a dynamic component, given by:

2 VCC ICC

PD (CL CPD)VCC f

n

At high frequencies ( 1 MHz), the quiescent current can be neglected.

17.Noise margin is a measure of the noise voltage that can be tolerated by a logic device input. In the HIGH state, it is

given by VNH VOH VIH. In the LOW state, it is given by VNL VIL VOL. CMOS devices generally have higher noise margins than TTL.

18.When interfacing two devices from different logic families, the driving gate must satisfy the voltage and current requirements of the load gates.

Summary 557

19.Input current in a CMOS gate is very low, due to its high input impedance. Thus, fanout is generally not a problem with CMOS loads.

20.CMOS devices that have the same values of VIH and VIL as TTL are considered to be TTL compatible, since they can be driven directly by TTL drivers.

21.A 74HC or 74HCT device can drive 10 LSTTL loads directly. To calculate fanout, we use the output currents for which the driving gate output voltages are defined.

22.A 74LS device can drive one or more 74HC devices, provided each 74HC input has a pull-up resistor (about 1 k to 10 k ) to supply sufficient voltage in the HIGH state.

23.A 74LS device can drive one or more 74HCT inputs directly.

24.Low-voltage CMOS (e.g., 74LVX or 74LCX) can be driven directly by a TTL device if the CMOS device is operated with a 3.3 V power supply. Noise margins are too small for a low-voltage CMOS driver to drive TTL loads.

25.74HC or 74HCT gates can be operated at a low value of VCC (e.g., 3 volts) and interfaced to a higher-voltage driver by an inverting or noninverting buffer, such as the 74HC4049 or 74HC4050. The interface buffer can tolerate relatively high input voltages (up to 15 V) and, if it shares the same supply voltage as the load gate, can provide correct input voltages to the load.

26.A bipolar transistor with a grounded emitter acts as an inverter or a digital switch. A HIGH at the base causes the transistor to conduct, pulling the collector to near-ground potential. If there is a pull-up resistor on the collector, there will be a HIGH state at the collector when the base is LOW.

27.The simplest TTL input is a transistor with its base con-

nected to VCC through a resistor. It can be treated as two diodes, back-to-back.

28.A TTL LOW input forward-biases the base-emitter junction of the input transistor, supplying a path to ground for input current.

29.A TTL HIGH input reverse-biases the base-emitter junction of the input transistor and forward-biases its base-collector junction. Input current in the HIGH state is restricted to reverse leakage current through the base-emitter junction.

30.An open TTL input is equivalent to a HIGH, as it provides no path to ground.

31.Some types of TTL gates, such as NAND, have multipleemitter input transistors. Any one input LOW acts as a LOW for the whole circuit.

32.Other TTL gates, such as NOR, have separate transistors for each input. Any HIGH input acts as a HIGH for the whole circuit.

33.An open-collector output has one output transistor that switches on a path to ground (logic LOW) when it is turned on. There is no separate internal circuit for a HIGH output. This must be provided by an external pull-up resistor.

34.Open-collector outputs can be used to parallel outputs (wired-AND), drive high-current loads, or interface to a circuit with a different power supply voltage than the driving gate.

35.A totem pole output has a transistor that switches on for a LOW output and another that switches on for a HIGH output. These output transistors are always in opposite states, except briefly during times when the output is changing states.

36.Totem pole outputs generate noise spikes on the power line of a circuit when they switch between logic states. These

558 C H A P T E R 1 1 • Logic Gate Circuitry

spikes can be amplified by inductance of the power line. Decoupling capacitors placed close to each device help minimize this problem.

37.TTL outputs should never be connected together, as they can be damaged when the outputs are in opposite states. (Too much output current flows.) The logic level under such conditions is not certain.

38.Gates with tristate outputs can generate logic LOW, logic HIGH, or high-impedance states. A high-impedance state is like an open circuit or electrical disconnection of the gate output from the circuit. In this state, both HIGHand LOWstate output transistors are off.

39.The operation of a tristate output is controlled by the state of a control input. In one control state, the output is either HIGH or LOW. In the opposite control state, the output is in the high-impedance state.

40.CMOS (complementary MOS) devices are based on n- channel and p-channel MOSFETs (metal-oxide-semiconduc- tor field effect transistors).

41.A MOSFET consists of a silicon substrate of a particular type of silicon (e.g., p-type), embedded with wells of the opposite type (e.g., n-type) that form the drain and source regions of the MOSFET. A gate electrode can bias the substrate to create a conduction channel between drain and source.

42.An n-channel enhancement mode MOSFET is biased on when its gate voltage exceeds its source voltage by a given amount called the threshold voltage.

43.A p-channel enhancement mode MOSFET is biased on when its gate voltage is less than its source voltage by a given amount called the threshold voltage.

44.An n-channel and p-channel MOSFET can be connected in such a way that one of the pair of MOSFETs is always on and one is always off. This connection is called a complementary pair and forms the basis for CMOS logic.

45.Logic functions, such as NAND and NOR, can be implemented with a complementary pair of MOSFETs for each in-

put, with the MOSFETs in series or parallel to VCC or ground, as required.

46.Many TTL families have been designed to incorporate Schottky barrier diodes, which limit the saturation of their transistors, allowing faster internal and output switching speeds.

47.Metal-gate CMOS has been superceded by high-speed (silicon-gate) CMOS, which has a smaller MOSFET size, resulting in faster switching and lower gate capacitance.

48.Speed-power product is a measure of the energy used by a gate. More advanced logic families have smaller values of speed-power product.

CMOS Complementary metal-oxide semiconductor. A logic family based on the switching of n- and p-channel metal-oxide- semiconductor field effect transistors (MOSFETs).

Cutoff mode The operating mode of a transistor when there is no collector or drain current flowing and the path from collector to emitter or drain to source is effectively an open circuit

Driving gate A gate whose output supplies current to the inputs of other gates.

ECL Emitter coupled logic. A high-speed logic family based on bipolar transistors.

Enhancement-mode MOSFET A MOSFET which creates a conduction path (a channel) between its drain and source terminals when the voltage between gate and source exceeds a specified threshold level.

Fanout The number of gate inputs that a gate output is capable of driving without possible logic errors.

Floating An undefined logic state, neither HIGH nor LOW.

High-speed (silicon-gate) CMOS A CMOS logic family with a smaller device structure and thus higher speed than standard (metal-gate) CMOS.

and dynamic supply currents.

Load gate A gate whose input current is supplied by the output of another gate.

MOSFET Metal-oxide-semiconductor field effect transistor. A MOSFET has three terminals—gate, source, and drain— which are analogous to the base, emitter, and collector of a bipolar junction transistor.

n-channel enhancement-mode MOSFET A MOSFET built on a p-type substrate with n-type drain and source regions. An n-type channel is created in the p-substrate during conduction.

Noise Unwanted electrical signal, often resulting from electromagnetic radiation.

Noise margin A measure of the ability of a logic circuit to tolerate noise.

n-type inversion layer The conducting layer formed between drain and source when an enhancement-mode n-channel MOSFET is biased ON. Also referred to as the channel.

Ohmic region The MOSFET equivalent of saturation. When a MOSFET is biased ON, it acts like a relatively low resistance, or “ohmically.”

Open-collector output A TTL output where the collector of the LOW-state output transistor is brought out directly to the output pin. There is no built-in HIGH-state output circuitry which allows two or more open collector outputs to be connected without possible damage.

p-channel enhancement-mode MOSFET A MOSFET

built on an n-type substrate with p-type drain and source regions. During conduction, a p-type channel is created in the n-substrate.

Phase splitter A transistor in a TTL circuit which ensures that the LOWand HIGH-state output transistors of a totem pole output are always in opposite phase (i.e., one ON, one OFF).

Power dissipation The electrical energy used by a logic circuit in a specified period of time. Abbreviation: PD

Propagation delay The time required for the output of a digital circuit to change states after a change at one or more of its inputs.

Saturation mode The operating mode of a bipolar transistor when an increase in base current will not cause a further increase in the collector current and the path from collector to emitter is very nearly (but not quite) a short circuit. This is the ON state of a transistor in a digital circuit.

Schottky barrier diode A specialized diode with a forward drop of about 0.4 V.

Schottky transistor A bipolar transistor with a Schottky diode across its base-collector junction, which prevents the transistor from going into deep saturation.

Schottky TTL A series of unsaturated TTL logic families based on Schottky transistors. Schottky TTL switches faster than standard TTL due to decreased storage time in its transistors.

Sinking A terminal on a gate or flip-flop is sinking current when the current flows into the terminal.

Sourcing A terminal on a gate or flip-flop is sourcing current when the current flows out of the terminal.

Speed-power product A measure of a logic circuit’s efficiency, calculated by multiplying its propagation delay by its power dissipation. Unit: picojoule (pJ)

Storage time Time required to transport stored charge away from the base region of a bipolar transistor before it can turn off.

Substrate The foundation of n- or p-type silicon on which an integrated circuit is built.

Threshold voltage, VGS(Th) The minimum voltage between gate and source of a MOSFET for the formation of the conducting inversion layer (channel).

Totem pole output A type of TTL output with a HIGH and a LOW output transistor, only one of which is active at any time.

from LOW to HIGH.

Tristate output An output having three possible states: logic HIGH, logic LOW, and a high-impedance state, in which the output acts as an open circuit.

TTL Transistor-transistor logic. A logic family based on bipolar transistors.

TTL Compatible Able to be driven directly by a TTL output. Usually implies voltage compatibility with TTL.

Wired-AND A connection where open-collector outputs of logic gates are wired together. The logical effect is the ANDing of connected functions.

Problem numbers set in color indicate more difficult problems: those with underlines indicate most difficult problems.

Section 11.1 Electrical Characteristics of Logic Gates

11.1Briefly list the advantages and disadvantages of TTL, CMOS, and ECL logic gates.

Section 11.2 Propagation Delay

11.2Explain how propagation delay is measured in TTL devices and CMOS devices. How do these measurements differ?

11.3Figure 11.65 shows the input and output waveforms of a logic gate. Use the graph to calculate tpHL and tpLH.

11.4The inputs of the logic circuit in Figure 11.66 are in state 1 in the following table. The inputs change to state 2, then to state 3.

a.Draw a timing diagram that uses the above changes of input state to illustrate the effect of propagation delay in the circuit.

b.Calculate the maximum time it takes for the output to change when the inputs change from state 1 to state 2.

c.Calculate the maximum time it takes for the output to change when the inputs change from state 2 to state 3.

FIGURE 11.65

Problem 11.3

Waveforms

FIGURE 11.66

Problems 11.4 and 11.5

Logic Circuit

11.5Repeat Problem 11.4 , parts b and c, for a 74HC00 NAND and a 74HC02 NOR gate.

Section 11.3 Fanout

11.6Calculate the maximum number of low-power Schottky TTL loads (74LSNN series) that a 74S86 XOR gate can drive.

11.7What is the maximum number of 74S32 OR gates that a 74LS00 NAND gate can drive?

11.8What is the maximum number of 74LS00 NAND gates that a 74S32 OR gate can drive?

11.9An LSTTL gate is driving seven LSTTL gate inputs, each equivalent to the load presented by a 74LS00 NAND input. Calculate the source and sink currents required from the driving gate.

11.10Calculate the current values for the circuits shown in Figure 11.67. For each circuit, state the logic level at the output of gate 1.