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Section 11.4 Power Dissipation

11.11The circuit in Figure 11.68 is constructed from the gates of a 74LS08 AND device. Calculate the power dissipation of the circuit for the following input logic levels:

A

B

C

D

E

a.

0

0

0

0

0

b.

1

1

0

1

1

c.

1

1

1

1

0

d.

1

1

1

1

1

FIGURE 11.68

Problems 11.11 to 11.13

Logic Circuit

11.12The gate outputs in Figure 11.68 are switching at an average frequency of 100 kHz, with an average duty cycle of 60%. Calculate the power dissipation if the gates are all 74S08 AND gates.

11.13The gates in Figure 11.68 are 74HC08A high-speed CMOS gates.

a.Calculate the power dissipation of the circuit if the input state is ABCDE 010101. (VCC 4.5 V, TA 25°C)

b.Calculate the circuit power dissipation if the outputs are switching at a frequency of 10 kHz, 50% duty cycle.

c.Repeat part b for a frequency of 2 MHz.

11.14The circuit in Figure 11.69 consists of two 74LS00 NAND gates (gates 4 and 5) and three 74LS02 NOR gates (gates 1, 2, and 3). When this circuit is actually built, there will be two unused NAND gates and one unused NOR gate in the device packages.

FIGURE 11.69

Problem 11.14

Logic Circuit

Problems 561

Calculate the maximum total power dissipation of the circuit when its input state is ABCDE 01100. Include all unused gates. (Connect unused gate inputs so that they will dissipate the least amount of power.)

11.15a. Calculate the no-load power dissipation of a single gate at 1 MHz for a 74HC00A quad 2-input NAND gate (VCC 5 V). (Neglect quiescent current.)

b.Calculate the percent change in power dissipation if the gate in part a of this question is operated with a new value of VCC 3.3 V. (f 1 MHz)

Section 11.5 Noise Margin

11.16Calculate the maximum noise margins, in both HIGH and LOW states, of:

a.A 74S00 NAND gate

b.A 74LS00 NAND gate

c.A 74AS00 NAND gate

d.A 74ALS00 NAND gate

e.A 74HC00 NAND gate (VCC 5 V)

f.A 74HCT00 NAND gate (VCC 5 V)

Section 11.6 Interfacing TTL and CMOS Gates

11.17Why can an LSTTL gate drive a 74HCT gate directly, but not a 74HC? Show calculations.

11.18Draw a circuit that allows an LSTTL gate to drive a 74HC gate. Explain briefly how it works.

11.19How many LSTTL loads (e.g., 74LS00) can a 74HC00A NAND gate drive? Use data sheet parameters to

support your answer. Assume VCC 4.5 V. Show all calculations.

Section 11.7 Internal Circuitry of TTL Gates

11.20In what logic state is an open TTL input? Why?

11.21Briefly describe the operation of the TTL open-collector inverter shown in Figure 11.20. What is the purpose of the diode?

11.22Briefly explain the operation of a multiple-emitter input transistor used in a TTL NAND gate. Describe how the transistor responds to various combinations of HIGH and LOW inputs.

11.23Draw a wired-AND circuit consisting of three opencollector NAND gates and an output pull-up resistor. The gate inputs are as follows:

Gate 1: Inputs A, B Gate 2: Inputs C, D Gate 3: Inputs E, F

Write the Boolean function of the circuit output.

11.24Calculate the minimum value of the pull-up resistor if the circuit drawn in Problem 11.23 is to drive a logic gate having input current IIL 0.8 mA and the NAND gates can sink 12 mA in the LOW output state. (Assume that VOL 0.4 V.)


562 C H A P T E R 1 1 • Logic Gate Circuitry

11.25Draw a circuit consisting only of open-collector gates whose Boolean expression is the product-of-sums expression

(A B)(C D)(E F)(G H).

11.26Is an open-collector TTL output likely to be damaged if shorted to ground? Why or why not?

11.27Is an open-collector TTL output likely to be damaged if shorted to VCC? Why or why not?

11.28Draw the totem pole output of a standard TTL gate.

11.29Refer to the TTL NAND gate in Figure 11.34.

a.Why are Q3 and Q4 never on at the same time (ideally)?

b.How does switching noise originate in a totem pole output? How can the problem be controlled?

11.30Explain briefly why two totem pole outputs should not be connected together.

11.31Two LED driver circuits are shown in Figure 11.70. For each circuit, calculate the current flowing when the LED is ON. Calculate the ratio between the LED

ON current and IOL or IOH of the inverter, whichever is appropriate for each circuit. State which is the best connection for LED driving and explain

why.

Vcc

330

74LS04

330

Vf 2 V

Vf 2 V

74LS04

FIGURE 11.70

Problem 11.31

LED drivers

11.32Calculate the current flowing when the lamp in Figure 11.71 is illuminated. Choose one of the following devices as a suitable driver: 74LS04, 74LS05 74LS06, 74LS16. Explain your choice. (Data sheets for these devices are found in Appendix C.)

24 V

LAMP 690

FIGURE 11.71

Problem 11.32

Lamp Driver

Section 11.8 Internal Circuitry of CMOS Gates

11.33State several precautions that should be taken to prevent electrostatic damage to MOSFET circuits.

11.34a. Draw the circuit symbols for an n-channel and a p- channel enhancement-mode MOSFET.

b.Describe the required bias conditions for each type of MOSFET in the cutoff and ohmic regions.

c.State the approximate channel resistance for a MOSFET in the cutoff and ohmic regions.

11.35Draw the circuit diagram of a CMOS AND gate. Derive the truth table of the gate by analyzing the operation of all the transistors under all possible input conditions.

11.36Repeat Problem 11.35 for a CMOS OR gate.

11.37Figure 11.72 shows a circuit that can switch two

analog signals to an automotive speedometer/tachometer. Each sensor produces an analog voltage proportional

to its measured quantity. Briefly explain how these analog signals are switched to the display output circuitry.

Section 11.9 TTL and CMOS Variations

11.38Briefly explain how a Schottky barrier diode can improve the performance of a transistor in a TTL circuit.

11.39Is the speed-power product of a TTL gate affected by the switching frequency of its output? Explain.

11.40Use data sheets to calculate the speed-power products of the following gates:

a.74LS00

b.74S00

c.74ALS00

d.74AS00

e.74HC00A (quiescent and 10 MHz)

f.74HCT00A (quiescent and 10 MHz)

g.74F00


FIGURE 11.72

Problem 11.37

Speedometer/Tachometer Switching Circuit

11.41Briefly explain the differences among the following highspeed CMOS logic families: 74HCNN, 74HC4NNN, 74HCTNN, and 74HCUNN.

11.42Assume that the power dissipation of a metal-gate or high-speed CMOS gate increases in proportion to the switching frequency of its output. Calculate the speed-

Answers to Section Review Problems

563

power product of the following gates at 2 MHz, 5 MHz, and 10 MHz:

a.4011B

b.74HCT04

c.74HCU04

A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S

Section 11.1

11.1VOH 2.7 V min. (We cannot expect typical values for VOH.) IOH 0.4 mA (The negative sign indicates that the current is leaving the gate. See Figure 11.2.)

Section 11.2

11.2 tpHL1 tpHL2 20 ns 22 ns 42 ns; tpLH2 22 ns

Section 11.3

11.3 Source currents: IOH, IIL; sink currents: IOL, IIH

Section 11.4

11.4CMOS draws very little current when its outputs are not switching. Since the majority of current is drawn when the outputs switch, the more often the outputs switch, the more current is drawn from the supply. This is the same as saying that power dissipation increases with frequency.

Section 11.5

11.5 VNH 1.98 V, VNL 0.66 V

Section 11.6

11.62.5 V. The interface buffer and load should have the same supply voltage so that the output voltage of the buffer and input voltage of the load are compatible.

Section 11.7a

11.7a. Provision of logic HIGH when output transistor is OFF b. Limitation of IOL when output transistor is ON

Section 11.7b

11.8 Rext 592 . Minimum standard value: 680

Section 11.7c

11.9When the output is HIGH, current flows to ground through a low-impedance path, causing IOH to exceed its rating.


564 C H A P T E R 1 1 • Logic Gate Circuitry

Section 11.7d

11.10The diode allows the base of Q4 to be pulled LOW through G, but will not allow a HIGH at G to turn it on. This keeps both output transistors OFF in the high-impedance state and allows them to be in opposite states when the output is enabled.

Section 11.7e

11.11Noninverting gates are actually double-inverting gates. They require an extra transistor stage to cancel the inversion introduced by NAND or NOR transistor logic.

Section 11.8a

11.12The thin oxide layer in the gate region can be damaged by overvoltage, such as that caused by electrostatic dis-

charge. If the oxide layer is damaged, it may no longer insulate the gate terminal from the MOSFET substrate, which causes the transistor to malfunction.

Section 11.8b

11.13It allows complementary operation with an n-channel MOSFET. Specifically, a gate voltage of 0 V turns OFF an n-channel device having a grounded source. The same voltage turns ON the p-channel device whose source is

tied to VCC. It does so by making the p-channel gatesource voltage more negative than the required threshold.

Section 11.9

11.14 13.36 pJ, 33.4 pJ, and 66.8 pJ.

C H A P T E R 12

Interfacing Analog

and Digital Circuits

O U T L I N E

12.1Analog and Digital Signals

12.2Digital-to-Analog Conversion

12.3Analog-to-Digital Conversion

12.4Data Acquisition

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

Define the terms “analog” and “digital” and give examples of each.

Explain the sampling of an analog signal and the effects of sampling frequency and quantization on the quality of the converted digital signal.

Draw the block diagram of a generic digital-to-analog converter (DAC) and circuits of a weighted resistor DAC and an R-2R ladder DAC.

Calculate analog output voltages of a DAC, given a reference voltage and a digital input code.

Configure an MC1408 integrated circuit DAC for unipolar and bipolar output, and calculate output voltage from known component values, reference voltage, and digital inputs.

Describe important performance specifications of a digital-to-analog converter.

Draw the circuit for a flash analog-to-digital converter (ADC) and briefly explain its operation.

Define “quantization error” and describe its effect on the output of an ADC.

Explain the basis of the successive approximation ADC, draw its block diagram, and briefly describe its operation.

Describe the operation of an integrator with constant input voltage.

Draw the block diagram of a dual slope (integrating) ADC and briefly explain its operation.

Explain the necessity of a sample and hold circuit in an ADC and its operation.

State the Nyquist sampling theorem and do simple calculations of maximum analog frequencies that can be accurately sampled by an ADC system.

Describe the phenomenon of aliasing and explain how it arises and how it can be remedied.

Interface an ADC0808 analog-to-digital converter to a CPLD-based state machine.

Design a 4-channel data acquisition system, including an ADC0808 analog- to-digital converter and a CPLD-based state machine.

565


566

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

Electronic circuits and signals can be divided into two main categories: analog and digital. Analog signals can vary continuously throughout a defined range. Digital signals

take on specific values only, each usually described by a binary number.

Many phenomena in the world around us are analog in nature. Sound, light, heat, position, velocity, acceleration, time, weight, and volume are all analog quantities. Each of these can be represented by a voltage or current in an electronic circuit. This voltage or current is a copy, or analog, of the sound, velocity, or whatever.

We can also represent these physical properties digitally, that is, as a series of numbers, each describing an aspect of the property, such as its magnitude at a particular time. To translate between the physical world and a digital circuit, we must be able to convert analog signals to digital and vice versa.

We will begin by examining some of the factors involved in the conversion between analog and digital signals, including sampling rate, resolution, range, and quantization.

We will then examine circuits for converting digital signals to analog, since these have a fairly standard form. Analog-to-digital conversion has no standard method. We will study several of the most popular: simultaneous (flash) conversion, successive approximation, and dual slope (integrating) conversion.

12.1 Analog and Digital Signals

K E Y T E R M S

Continuous Smoothly connected. An unbroken series of consecutive values with no instantaneous changes.

Discrete Separated into distinct segments or pieces. A series of discontinuous values.

Analog A way of representing some physical quantity, such as temperature or velocity, by a proportional continuous voltage or current. An analog voltage or current can have any value within a defined range.

Digital A way of representing a physical quantity by a series of binary numbers.

A digital representation can have only specific discrete values.

Analog-to-digital converter A circuit that converts an analog signal at its input to a digital code. (Also called an A-to-D converter, A/D converter, or ADC.)

Digital-to-analog converter A circuit that converts a digital code at its input to an analog voltage or current. (Also called a D-to-A converter, D/A converter, or DAC.)

Electronic circuits are tools to measure and change our environment. Measurement instruments tell us about the physical properties of objects around us. They answer questions such as “How hot is this water?”, “How fast is this car going?”, and “How many electrons are flowing past this point per second?” These data can correspond to voltages and currents in electronic instruments.

If the internal voltage of an instrument is directly proportional to the quantity being measured, with no breaks in the proportional function, we say that it is an analog voltage. Like the property being measured, the voltage can vary continuously throughout a defined range.

For example, sound waves are continuous movements in the air. We can plot these movements mathematically as a sum of sine waves of various frequencies. The patterns of magnetic domains on an audio tape are analogous to the sound waves that produce them and electromagnetically represent the same mathematical functions. When the tape is played, the playback head produces a voltage that is also proportional to the original sound waves. This analog audio voltage can be any value between the maximum and minimum voltages of the audio system amplifier.