Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

FIGURE 12.3

Effect of Sampling Frequency

SECTION 12.1 REVIEW PROBLEM

12.1An analog signal has a range of 0 to 24 mV. The range is divided into 32 equal steps for conversion to a series of digital codes. How many bits are in the resultant digital codes? What is the resolution of the A/D converter?

12.2Digital-to-Analog Conversion

K E Y T E R M

Full scale The maximum analog reference voltage or current of a digital-to-

analog converter.

Figure 12.4 shows the block diagram of a generalized digital-to-analog converter. Each digital input switches a proportionally weighted current on or off, with the current for the MSB being the largest. The second MSB produces a current half as large. The current generated by the third MSB is one quarter of the MSB current, and so on.

These currents all sum at the operational amplifier’s (op amp’s) inverting input. The total analog current for an n-bit circuit is given by:

Ia bn 12n 1 n b222 b121 b020 Iref

2

The bit values b0, b1, . . . bn can be only 0 or 1. The function of each bit is to include or exclude a term from the general expression.

FIGURE 12.4

Analysis of a Generalized

Digital-to-Analog Converter

The op amp acts as a current-to-voltage converter. The analysis, illustrated in Figure 12.4b, is the same as for an inverting op amp circuit with a constant input current.

The input impedance of the op amp is the impedance between its inverting ( ) and noninverting ( ) terminals. This value is very large, on the order of 2 M . If this is large compared to other circuit resistances, we can neglect the op amp input current, Iin.

This implies that the voltage drop across the input terminals is very small; the inverting and noninverting terminals are at approximately the same voltage. Since the noninverting input is grounded, we can say that the inverting input is “virtually grounded.”

Current IF flows in the feedback loop, through resistor RF. Since Ia Iin IF 0 and

Iin 0, then IF Ia. By Ohm’s law, the voltage across RF is given by VF Ia RF. The feedback resistor is connected to the output at one end and to virtual ground at the other. The op

amp output voltage is measured with respect to ground. The two voltages are effectively in parallel. Thus, the output voltage is the same as the voltage across the feedback resistor, with a polarity opposite to VF, calculated above.

Solution The analog current of a 4-bit converter is:

Ia b3 23 b2422 b1 21 b0 20 2 Iref

8b3 4b2 2b1 b0 (1 mA) 16

Example 12.1 suggests an easy way to calculate D/A analog current. Ia is a fraction of

the reference current Iref. The denominator of the fraction is 2n for an n-bit converter. The numerator is the decimal equivalent of the binary input. For example, for input b3b2b1b0

0111, Ia (7/16)(Iref).

Note that when b3b2b1b0 1111, the analog current is not the full value of Iref, but 15/16 of it. This is one least significant bit less than full scale.

This is true for any D/A converter, regardless of the number of bits. The maximum analog current for a 5-bit converter is 31/32 of full scale. In an 8-bit converter, Ia cannot exceed 255/256 of full scale. This is because the analog value 0 has its own code. An n-bit converter has 2n input codes, ranging from 0 to 2n 1.

The difference between the full scale (FS) of a digital-to-analog converter and its maximum output is the resolution of the converter. Since the resolution is the smallest change in output, equivalent to a change in the least significant bit, we can define the maximum output as FS 1 LSB. (As an example, in the case of an 8-bit converter FS 1 LSB 255/256 Iref.)

SECTION 12.2A REVIEW PROBLEM

12.2Calculate the range of analog voltage of a 4-bit D/A converter having values of Iref 1 mA and RF 10 k . Repeat the calculation for an 8-bit D/A converter.

Weighted Resistor D/A Converter

Figure 12.5 shows the circuit of a 4-bit weighted resistor D/A converter. The heart of this circuit is a parallel network of binary-weighted resistors. The MSB has a resistor value of R. Successive branches have resistor values that double with each bit: 2R, 4R, and 8R. The branch currents decrease by halves with each descending bit value.

FIGURE 12.5

Weighted Resistor D-to-A

Converter

The bit inputs, b3, b2, b1, and b0, are either 0 V or Vref. When the corresponding bits are

HIGH, the branch currents are:

I3 Vref/R

I2 Vref/2R

I1 Vref/4R

I0 Vref/8R

The sum of branch currents gives us the analog current Ia.

We can calculate the analog voltage by Ohm’s law:

V2 Ia RF Ia (R/2)

The choice of RF R/2 makes the analog output a binary fraction of Vref.

The weighted resistor DAC is seldom used in practice. One reason is the wide range of resistor values required for a large number of bits. Another reason is the difficulty in obtaining resistors whose values are sufficiently precise.

A 4-bit converter needs a range of resistors from R to 8R. If R 1 k , then 8R 8 k . An 8-bit DAC must have a range from 1 k to 128 k . Standard value resistors are specified to two significant figures; there is no standard 128-k resistor. We would need to use relatively expensive precision resistors for any value having more than two significant figures.

Another DAC circuit, the R-2R ladder, is more commonly used. It requires only two values of resistance for any number of bits.

SECTION 12.2B REVIEW PROBLEM

12.3The resistor for the MSB of a 12-bit weighted resistor D/A converter is 1 k . What is the resistor value for the LSB?

R-2R Ladder D/A Converter

Figure 12.6 shows the circuit of an R-2R ladder D/A converter. Like the weighted resistor DAC, this circuit produces an analog current that is the sum of binary-weighted currents. An operational amplifier converts the current to a proportional voltage.

FIGURE 12.6

R-2R Ladder DAC

The circuit requires an operational amplifier with a high slew rate. Slew rate is the rate at which the output changes after a step change at the input. If a standard op amp (e.g., 741C) is used, the circuit will not accurately reproduce changes introduced by large changes in the digital input.

The method of generating the analog current for an R-2R ladder DAC is a little less obvious than for the weighted resistor DAC. As the name implies, the resistor network is a ladder that has two values of resistance, one of which is twice the other. This circuit is expandable to any number of bits simply by adding one resistor of each value for each bit.

The analog output is a function of the digital input and the value of the op amp feed-

back resistor. If logic HIGH Vref, logic LOW 0 V, and RF R, the analog output is given by:

One way to analyze this circuit is to replace the R-2R ladder with its Thévenin equivalent circuit and treat the circuit as an inverting amplifier. Figure 12.7 shows the equivalent circuit for the input code b3b2b1b0 1000.

Figure 12.8a shows the equivalent circuit of the R-2R ladder when b3b2b1b0 1000.

All LOW bits are grounded, and the HIGH bit connects to Vref. We can reduce the network to two resistors by using series and parallel combinations.

The two resistors at the far left of the ladder are in parallel: 2R 2R R. This equivalent resistance is in series with another: R R 2R. The new resistance is in parallel with yet another: 2R 2R R. We continue this process until we get the simplified circuit shown in Figure 12.8b.

FIGURE 12.7

Equivalent Circuit for b3b2b1b0 1000

FIGURE 12.8

R-2R Circuit Analysis for b3b2b1b0 1000

Next, we find the Thévenin equivalent of the simplified circuit. To find ETh, calculate the terminal voltage of the circuit, using voltage division.

2R

ETh Vref Vref /2

2R 2R

RTh is the resistance of the circuit, as measured from the terminals, with the voltage source short-circuited. Its value is that of the two resistors in parallel: RTh 2R 2R R.

N O T E

The value of the Thévenin resistance of the R-2R ladder will always be R, regardless of the digital input code. This is because we short-circuit any voltage sources when we make this calculation, which grounds the corresponding bit resistors. The other resistors are already grounded by logic LOWs. We reduce the circuit to a single resistor, R, by parallel and series combinations of R and 2R. Figure 12.9 shows the equivalent circuit.

FIGURE 12.9

Equivalent Circuit for Calculating RTh

On the other hand, the value of ETh will be different for each different binary input. It will be the sum of binary fractions of the full-scale output voltage, as previously calculated for the generic DAC.

Similar analysis of the R-2R ladder shows that when b3b2b1b0 0100, Va Vref/4, when b3b2b1b0 0010, Va Vref/8, and when b3b2b1b0 0001, Va Vref/16.

If two or more bits in the R-2R ladder are active, each bit acts as a separate voltage source. Analysis becomes much more complicated if we try to solve the network as we did for one active bit.

There is no need to go through a tedious circuit analysis to find the corresponding analog voltage. We can simplify the process greatly by applying the Superposition theorem. This theorem states that the effect of two or more sources in a network can be determined by calculating the effect of each source separately and adding the results.

The Superposition theorem suggests a generalized equivalent circuit of the R-2R ladder DAC. This is shown in Figure 12.10. A Thévenin equivalent source and resistance corresponds to each bit. The source and resistance are switched in and out of the circuit, depending on whether or not the corresponding bit is active.

FIGURE 12.10

Equivalent Circuit of R-2R DAC