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62	C H A P T E R	3 • Boolean Algebra and Combinational Logic
FIGURE 3.7		A		AC
FIGURE 3.7		A		AC
Logic Diagram for
Y AC BD AD				BD
		B		BD
		B
		C
				AD




		D

			a. ANDs first
			a. ANDs first

Y AC BD AD

b.Combine ANDs in an OR gate

FIGURE 3.8

Logic Diagram for Y (A B) (A C D) (B C)

When the expression has OR functions in parentheses, we synthesize the ORs ﬁrst, as for the expression Y (A B)(A C D)(B C). Figure 3.8 shows this process. In the ﬁrst step, we synthesize three OR gates for the terms (A B), (A C D), and (B C). We then combine these terms in a 3-input AND gate.

(A B)

(A C D)

C D

(B C)

		a. ORs first
	A
	B
	C	Y (A B)(A C D)(B C)
	D	Y (A B)(A C D)(B C)
	D

	b. Combine ORs in an AND gate

EXAMPLE 3.4	Synthesize the logic diagrams for the following Boolean expressions:
	1. P QRS ST
	2. X (W Z Y)V (W V)Y

Solution

1.Recall that a bar over two variables acts like parentheses. Thus the QRS term is synthe-

sized from a NAND, then an AND, as shown in Figure 3.9a. Also shown is the second AND term, ST.

FIGURE 3.9

Example 3.4

Logic Diagram of

P QRS ST

FIGURE 3.10

Example 3.4

Logic Diagram for X

(W Z Y)V (W V)Y

3.1 • Boolean Expressions, Logic Diagrams and Truth Tables

Figure 3.9b shows the terms combined in an OR gate.

Q	QRS
R	RS
S
	S
	ST
T
	a. Combine inputs (NAND, then AND)
Q	QRS
R	RS	P QRS ST
S

b.First and second level gates combined in and OR

2.Figure 3.10 shows the synthesis of the second logic diagram in three stages. Figure 3.10a shows how the circuit inputs are ﬁrst combined in two OR gates. We do this ﬁrst because the ORs are in parentheses. In Figure 3.10b, each of these functions is combined in an AND gate, according to the normal order of precedence. The AND outputs are combined in a ﬁnal OR function, as shown in Figure 3.10c.

W		W Z Y
Z
Y
	W	W V
		W V
V
	a. ORs first (parentheses)

W	W Z Y
Z
Y	V
	Y
W	W V
V

(W Z Y)V

(W V)Y

b. Combine with ANDs (order of precedence)

W	W Z Y
Z
Y	V
	Y
W	W V
V

(W Z Y)V

X (W X Y)V (W V)Y

(W V)Y

c. Find output (OR)

C H A P T E R

3 • Boolean Algebra and Combinational Logic

EXAMPLE 3.5

Use DeMorgan’s theorem to modify the Boolean equation in part 1 of Example 3.4 so that

there is no bar over any group of variables. Redraw Figure 3.9b to reﬂect the change.

Solution

P QRS ST Q(R S) ST

Figure 3.11a shows the modiﬁed logic diagram. The levels of gating could be further

reduced from three to two (not counting input inverters) by “multiplying through” the

parentheses to yield the expression:

P QR QS ST

Figure 3.11b shows the logic diagram for this form. We will examine this simpliﬁca-

tion procedure more formally in a later section of this chapter.

Q(R

P Q(R

S) ST

a. Logic diagram of P Q(R

S) ST

P QR QS ST

b. Logic diagram of P QR QS

FIGURE 3.11

Example 3.5: Reworking Figure 3.9b

FIGURE 3.12

Logic Diagram for AB C

Truth Tables from Logic Diagrams or Boolean Expressions

There are two basic ways to ﬁnd a truth table from a logic diagram. We can examine the output of each gate in the circuit and develop its truth table. We then use our knowledge of gate properties to combine these intermediate truth tables into the ﬁnal output truth table. Alternatively, we can develop a Boolean expression for the logic diagram and by examining the expression ﬁll in the truth table in a single step. The former method is more thorough and probably easier to understand when you are learning the technique. The latter method is more efﬁcient, but requires some practice and experience. We will look at both.

Examine the logic diagram in Figure 3.12. Since there are three binary inputs, there will be eight ways those inputs can be combined. Thus, we start by making an 8-line truth table, as in Table 3.1.

A	AB
A
B

AB C

3.1 • Boolean Expressions, Logic Diagrams and Truth Tables

The OR gate output will describe the function of the whole circuit. In order to assess the OR function, we must ﬁrst evaluate the AND output. We add a column to the truth table for the AND gate and look for the lines in the table where both A AND B equal logic 1 (in this case, the last two rows). For these lines, we write a 1 in the AB column. Next, we look at the values in column C and the AB column. If there is a 1 in either column, we write a 1 in the column for the ﬁnal output.

Table 3.1 Truth Table for Figure 3.12

A	B	C	AB	AB C

0	0	0	0	0
0	0	1	0	1
0	1	0	0	0
0	1	1	0	1
1	0	0	0	0
1	0	1	0	1
1	1	0	1	1
1	1	1	1	1

EXAMPLE 3.6 Derive the truth table for the logic diagram shown in Figure 3.13.

FIGURE 3.13

Example 3.6

Logic Diagram

Solution The Boolean equation for Figure 3.13 is (A B)(A C). We will create a column for each input variable and for each term in parentheses, as well as a column for the ﬁnal output. Table 3.2 shows the result. For the lines where A OR B is 0, we write a 1 in the (A B) column. Where A OR C is 1, we write a 1 in the (A C) column. For the lines where there is a 1 in both the (A B) AND (A C) columns, we write a 1 in the ﬁnal output column.

Table 3.2 Truth Table for Figure 3.13

A B C			(A B)	(A C)	(A B)(A C)

0	0	0	1	0	0
0	0	1	1	1	1
0	1	0	1	0	0
0	1	1	1	1	1
1	0	0	1	1	1
1	0	1	1	1	1
1	1	0	0	1	0
1	1	1	0	1	0

66 C H A P T E R 3 • Boolean Algebra and Combinational Logic

FIGURE 3.14

Logic Diagram

Another approach to ﬁnding a truth table involves analysis of the Boolean expression of a logic diagram. The logic diagram in Figure 3.14 can be described by the Boolean expression Y ABC A C B D.

We can examine the Boolean expression to determine that the ﬁnal output of the circuit will be HIGH under one of the following conditions:

1.A 0 AND B 1 AND C 1;

2.A 0 AND C 0;

3.B 0 AND D 0.

All we have to do is look for these conditions in the truth table and write a 1 in the output column whenever a condition is satisﬁed. Table 3.3 shows the result of this analysis with each line indicating which term, or terms, contribute to the HIGH output.

Table 3.3 Truth Table for Figure 3.14