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FIGURE 2.46
Problem 2.31: Gasoline Level Circuit
“Hi-Z” How do the enable properties of these gates differ from gates such as AND and NAND?
Answers to Section Review Problems |
55 |
Section 2.6 Integrated Circuit Logic Gates
2.35Name two logic families used to implement digital logic functions. How do they differ?
2.36List the industry-standard numbers for a quadruple 2-input NAND gate in low power Schottky TTL, CMOS, and high-speed CMOS technologies.
2.37Repeat Problem 2.36 for a quadruple 2-input NOR gate. How does each numbering system differentiate between the NAND and NOR functions?
2.38List six types of packaging that a logic gate could come in.
A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S
Section 2.1
2.1 AND: “A AND B AND C AND D must be HIGH to make Y HIGH.” 2.2. OR: “A OR B OR C OR D must be HIGH to make Y HIGH.”
Section 2.2
2.3 When the switch is open, it provides a logic HIGH because of the pull-up resistor. A closed switch is LOW, due to the connection to ground.
Section 2.3
2.4 XOR; |
2.5 NAND; |
2.6 NOR; |
2.7 XNOR. |
Section 2.4
2.8 Y A B C D
Section 2.5
2.9 An AND needs two HIGH inputs to make a HIGH output. If the Control input is LOW, the output can never be HIGH; the output remains LOW. An OR output is HIGH if one input is HIGH. If the Control input is HIGH, the output is always HIGH, regardless of the level at the Signal input. In both cases, the output is “stuck” at one level, signifying that the gate is inhibited.
Section 2.6
2.10 Viewed from above, with the notch in the package away from you, pin 1 is on the left side at the far end. The pins are numbered counterclockwise from that point.
C H A P T E R 3
Boolean Algebra and
Combinational Logic
O U T L I N E
3.1Boolean Expressions, Logic Diagrams, and Truth Tables
3.2Sum-of-Products (SOP) and Product- of-Sums (POS) Forms
3.3Theorems of Boolean Algebra
3.4Simplifying SOP and POS Expressions
3.5Simplification by the Karnaugh Map Method
C H A P T E R O B J E C T I V E S
Upon successful completion of this chapter you will be able to:
•Explain the relationship between the Boolean expression, logic diagram, and truth table of a logic gate network and be able to derive any one from either of the other two.
•Draw logic gate networks in such a way as to cancel out internal inversions automatically (bubble-to-bubble convention).
•Write the sum of products (SOP) or product of sums (POS) forms of a Boolean equation.
•Use rules of Boolean algebra to simplify the Boolean expressions derived from logic diagrams and truth tables.
•Apply the Karnaugh map method to reduce Boolean expressions and logic circuits to their simplest forms.
In Chapter 3, we will examine the rudiments of combinational logic. A combinational logic circuit is one in which two or more gates are connected together to combine several Boolean inputs. These circuits can be represented several ways, as a logic diagram,
truth table, or Boolean expression.
A Boolean expression for a network of logic gates is often not in its simplest form. In such a case, we may be using more components than would be required for the job, so it is of benefit to us if we can simplify the Boolean expression. Several tools are available to us, such as Boolean algebra and a graphical technique known as Karnaugh mapping. We can also simplify the Boolean expression by taking care to draw the logic diagrams in such a way as to automatically eliminate inverting functions within the circuit. ■
57
58 C H A P T E R 3 • Boolean Algebra and Combinational Logic
3.1 Boolean Expressions, Logic Diagrams and Truth Tables
K E Y T E R M S
Logic gate network Two or more logic gates connected together.
Logic diagram A diagram, similar to a schematic, showing the connection of logic gates.
Combinational logic Digital circuitry in which an output is derived from the combination of inputs, independent of the order in which they are applied.
Combinatorial logic Another name for combinational logic.
In Chapter 2, we examined the functions of single logic gates. However, most digital circuits require multiple gates. When two or more gates are connected together, they form a logic gate network. These networks can be described by a truth table, a logic diagram (i.e., a circuit diagram), or a Boolean expression. Any one of these can be derived from any other.
A digital circuit built from gates is called a combinational (or combinatorial) logic circuit. The output of a combinational circuit depends on the combination of inputs. The inputs can be applied in any sequence and still produce the same result. For example, an AND gate output will always be HIGH if all inputs are HIGH, regardless of the order in which they became HIGH. This is in contrast to sequential logic, in which sequence matters; a sequential logic output may have a different value with two identical sets of inputs if those inputs were applied in a different order. We will study sequential logic in a later chapter.
Boolean Expressions from Logic Diagrams
K E Y T E R M S
Bubble-to-bubble convention The practice of drawing gates in a logic diagram so that inverting outputs connect to inverting inputs and noninverting outputs connect to noninverting inputs.
Order of precedence The sequence in which Boolean functions are performed, unless otherwise specified by parentheses.
Writing the Boolean expression of a logic gate network is similar to finding the expression for a single gate. The difference is that in a multiple gate network, the inputs will usually not consist of single variables, but compound expressions that represent outputs of previous gates.
These compound expressions are combined according to the same rules as single variables. In an OR gate, with inputs x and y, the output will always be x y regardless of whether x and y are single variables (e.g., x A, y B, output A B) or compound expressions (e.g., x AB, y AC, output AB AC).
Figure 3.1 shows a simple logic gate network, consisting of a single AND and a single OR gate. The AND gate combines inputs A and B to give the output expression AB. The OR combines the AND function and input C to yield the compound expression
AB C.
A |
AB |
B |
Y AB C |
C |
FIGURE 3.1
Boolean Expression from a Gate Network
3.1 • Boolean Expressions, Logic Diagrams and Truth Tables |
59 |
EXAMPLE 3.1
FIGURE 3.2
Example 3.1
Derive the Boolean expression of the logic gate network shown in Figure 3.2a.
A
B
Y |
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C |
|
D |
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a. Logic gate network |
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Solution |
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A |
AB |
B |
Y AB CD |
C |
CD |
D |
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b. Boolean expression from logic gate network |
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Figure 3.2b shows the gate network with the output terms indicated for each gate. The AND and NAND functions are combined in an OR function to yield the output expression:
Y AB CD
The Boolean expression in Example 3.1 includes a NAND function. It is possible to |
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draw the NAND in its DeMorgan equivalent form. If we choose the gate symbols so that |
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outputs with bubbles connect to inputs with bubbles, we will not have bars over groups of |
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variables, except possibly one bar over the entire function. In a circuit with many inverting |
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functions (NANDs and NORs), this results in a cleaner notation and often a clearer idea of |
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the function of the circuit. We will follow this notation, which we will refer to as the bubble- |
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to-bubble convention, as much as possible. |
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EXAMPLE 3.2 |
Redraw the circuit in Figure 3.2 to conform to the bubble-to-bubble convention. Write the |
Boolean expression of the new logic diagram. |
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Solution |
A |
AB |
B |
Y AB C D |
C |
D |
D |
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FIGURE 3.3 |
Example 3.2
Using DeMorgan Equivalents to Simplify a Circuit
Figure 3.3 shows the new circuit. The NAND has been converted to its DeMorgan equivalent so that its active-HIGH output drives an active-HIGH input on the OR gate. The
new Boolean expression is Y AB C D. |
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Boolean functions are governed by an order of precedence. Unless otherwise specified, AND functions are performed first, followed by ORs. This order results in a form similar to that of linear algebra, where multiplication is performed before addition, unless otherwise specified.
60 C H A P T E R 3 • Boolean Algebra and Combinational Logic
Figure 3.4 shows two logic diagrams, one whose Boolean expression requires parentheses and one that does not.
A
B
C
A
B
C
FIGURE 3.4
Order of Precedence
AB
AB AC
AC
a. No parentheses required (AND, then OR)
A B
(A B) (A B C)
A B C
b. Parentheses required (OR, then AND)
The AND functions in Figure 3.4a are evaluated first, eliminating the need for parentheses in the output expression. The expression for Figure 3.4b requires parentheses since the ORs are evaluated first.
EXAMPLE 3.3
FIGURE 3.5
Example 3.5
Order of Precedence
Write the Boolean expression for the logic diagrams in Figure 3.5.
A
1
B
3 Y
2
C
a.
P
1
Q
3 S
2
R
b.
Solution Examine the output of each gate and combine the resultant terms as required.
Figure 3.5a: Gate 1: A B
Gate 2: B C
Gate 3: Y Gate 1 Gate2 A B B C
Figure 3.5b: Gate 1: P Q P Q
Gate 2: Q R
Gate 3: S Gate1 Gate2 (P Q)(Q R) (P Q)(Q R)
3.1 • Boolean Expressions, Logic Diagrams and Truth Tables |
61 |
Note that when two bubbles touch, they cancel out, as in the doubly inverted P input or the connection between the outputs of gates 1 and 2 and the inputs of gate 3. In the re-
sultant Boolean expression, bars of the same length cancel; bars of unequal length do not.
SECTION 3.1A REVIEW PROBLEM
3.1Write the Boolean expression for the logic diagrams in Figure 3.6, paying attention to the rules of order of precedence.
A
B
Y
C
D
a.
W
X
OUT
Y
Z
b.
FIGURE 3.6
Section Review Problem 3.1
Logic Diagrams from Boolean Expressions
K E Y T E R M S
Levels of gating The number of gates through which a signal must pass from input to output of a logic gate network.
Double-rail inputs Boolean input variables that are available to a circuit in both
true and complement form.
Synthesis The process of creating a logic circuit from a description such as a Boolean equation or truth table.
We can derive a logic diagram from a Boolean expression by applying the order of precedence rules. We examine an expression to create the first level of gating from the circuit inputs, then combine the output functions of the first level in the second level gates, and so forth. Input inverters are often not counted as a gating level, as we usually assume that each variable is available in both true (noninverted) and complement (inverted) form. When input variables are available to a circuit in true and complement form, we refer to them as double-rail inputs.
The first level usually will be AND gates if no parentheses are present, OR gates if parentheses are used. (Not always, however; parentheses merely tell us which functions to synthesize first.) Although we will try to eliminate bars over groups of variables by use of DeMorgan’s theorems and the bubble-to-bubble convention, we should recognize that a bar over a group of variables is the same as having those variables in parentheses.
Let us examine the Boolean expression Y AC BD AD. Order of precedence tells us that we synthesize the AND functions first. This yields three 2-input AND gates, with outputs AC, BD, and AD, as shown in Figure 3.7a. In the next step, we combine these AND functions in a 3-input OR gate, as shown in Figure 3.7b.