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610

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

FIGURE 12.42

eoc/sc,oe,en

State Diagram for Continuous-

start

Convert ADC Controller

X/100

X /000

store

wait 1

1/000

X /010

0/000

read

wait 2

1/011

0/000

FIGURE 12.43

Simulation of Continuous-

Conversion ADC Controller

EXAMPLE 12.13

From the ADC0808 data sheet extract in Figure 12.37, determine the number of clock cy-

cles required for the conversion of an analog signal.

Solution For a clock frequency of 640 kHz, typical conversion time is given as 100 s.

640 103 clock cycles (100 10 6 seconds) 64 clock cycles

second

EXAMPLE 12.14

Calculate the highest-frequency analog input that can be accurately converted by an

ADC0808 controlled by a state machine represented by the state diagram of Figure 12.42

if the system clock frequency is 787 kHz.

Solution One conversion cycle, Ts, requires 64 clock cycles for the ADC and an

overhead of 13 clocks 2 s for the state machine for a total of 77 clock cycles 2

s. (Start to wait1 requires one clock cycle. An additional 8 cycles 2 s are needed

before eoc goes LOW. According to Note 7 in Figure 12.37, the ADC conversion is

complete one clock cycle before EOC goes HIGH. From this point back to start is 4

clocks.)

12.4 •

Data Acquisition

611

T =

1

× 77 clock cycles + 2

µs = 99.8 × 10−6 seconds

× 103

s

787

clock cycles/second

fs

=

1

=

1

= 10.02 kHz

× 10−6

Ts

99.8

s

According to the Nyquist sampling theorem, the maximum-frequency component of the sampled analog signal is fmax fs/2 10.02 kHz/2 5.01 kHz. This is of the same or-

der of magnitude as a telephone-quality audio signal.

CPLD-Based Data Acquisition Network

Figure 12.44 shows a data acquisition system that continuously converts and stores data from four analog channels. All the circuitry within the broken line is contained within a single CPLD, such as the Altera EPM7128SLC84. The operation is similar to the system in

Analog sources

ADC0808

IN0

D[7..0]

IN1

IN2

IN3

IN4

ADD A

ADD B

IN5

ADD C

IN6

IN7

CLK

CLK

ALE/START

OE

EOC

CONTROLLER

DECODER

OE

EOC

Y0

SC LATCH_EN

EN

Y1

RESET

D1

Y2

CLK

CNT_EN

D0

Y3

CTR DIV 4

CNT_EN

Q1

Q0

VCC

RESET

CLK

RESET

FIGURE 12.44

4-Channel Data Acquisition System

Octal latch

D[7..0] Q[7..0] EN

RESET

Octal latch

D[7..0] Q[7..0] EN

RESET

Octal latch

D[7..0] Q[7..0] EN

RESET

Octal latch

D[7..0] Q[7..0]

EN

RESET

CPLD

Q0[7..0]

Q1[7..0]

Q2[7..0]

Q3[7..0]

612

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

Figure 12.38, except that with multiple latches in the circuit, a counter and decoder are required to keep track of the selected channel.

The controller, whose state diagram is shown in Figure 12.45, generates the same control signals for the ADC as the system in Figure 12.38. When the conversion is complete and the controller detects a LOW on its eoc input, it reads the ADC output and transfers the contents to the selected 8-bit latch. The latch is selected, via the decoder, by the value of the counter (e.g., Q1Q0 11 selects analog input channel 3, decoder output Y3, and latch 3). The selected latch input is enabled (i.e., made transparent) by the controller during the transition from wait2 to read. At all other times all decoder outputs are LOW, disabling all latches, thus placing them in store mode. After the ADC data have been stored, the controller sets cnt_en HIGH, which allows the counter to be incremented on the next clock pulse. The next channel is now ready for a convert-and-store cycle. After all channels have been sampled, converted, and stored, the cycle begins again at channel 0 and continues indefinitely.

eoc/sc,oe,cnt_en, latch_en

X /0000

start

X/1000

incr

wait 1

1/0000

X /0010

0/0000

store

wait 2

X /0100

read

1/0101

0/0000

FIGURE 12.45

State Diagram for 4-channel Data Acquistion System

Figure 12.46 shows a simulation of the controller, counter, and decoder for the data acquisition system of Figure 12.44. During the read-and-store part of the cycle, only one of the latch enables, y0 to y3, is active when oe is active. The number of the active latch enable is the same as the counter value on the second last waveform. The last line in the simulation (controller|outputs3.Q) is the cnt_en line from the controller to the counter. The counter is incremented on the first positive edge of the clock after this line goes HIGH. This point is indicated by the cursor line on the transition from channel 1 to channel 2.

The circuit in Figure 12.44 could be expanded to convert all eight analog channels from the ADC, but the chosen CPLD (EPM7128SLC84) does not have enough I/O pins. Eight 8-bit latch outputs require 64 pins; the CPLD only has 60 user I/Os. An 8-channel system could be implemented if it used eight external latches, such as eight 74HC373 octal latches, or internal latches on a different CPLD. Note that the CPLD has enough logic cells to implement the system, just not enough I/O pins. The identical device in a different package (EPM7128SQC100; 100-pin quad flat-pack) can accommodate the entire system.

For an 8-channel system, the counter would need to be expanded to 3 bits and the decoder to a 3-line-to-8-line device.

Summary 613

FIGURE 12.46

Simulation of 4-channel Data Acquisition System

SECTION 12.4 REVIEW PROBLEM

12.8Calculate the highest-frequency component of an analog signal that can be accurately converted by the 4-channel data acquisition system in Figure 12.44. Assume the system clock is running at 787 kHz.

S U M M A R Y

01. An analog system can represent a physical property (e.g., temperature, pressure, or velocity) by a proportional voltage or current. The mathematical function describing the analog voltage or current is continuous throughout a defined range.

02. A digital system can represent a physical property by a series of binary numbers of a fixed bit size.

03. Digital representations of data are not subject to the same distortions as analog representations. They are also easier to store and reproduce than analog.

04. The quality of a digital representation depends on the sampling frequency and quantization (number of bits) of the system that converts an analog input to a digital output.

05. The resolution of a system is a function of the number of bits in its digital representation. A greater number of bits implies that the sampled analog input can be broken up into more, smaller segments, allowing each segment to more closely approximate the original input value.

06. A digital-to-analog converter (DAC) uses electronic switches to sum binary-weighted currents to a total analog output current. Analog current can be calculated by:

bn 12n 1 bn 2 2n 2 . . . b222 b121 b020

Ia Iref

or, more simply:

I

=

digital code

I

a

2n

ref

for an n-bit DAC, where bn 1bn 2 … b2b1b0 is the digital input code,

Ia is the analog output current, and

Iref is the DAC reference (full scale) current.

07. The maximum output of a DAC is full scale (FS) minus the value represented by a change in the least significant bit of the input (FS 1 LSB). For example, for a 4-bit converter (1 LSB 1/16 FS), the maximum output is (FS1/16 FS) 15/16 FS. For an 8-bit converter (1 LSB 1/256 FS), the maximum output is (FS 1/256 FS) 255/256 FS.

614

C H A P T E R 1 2 • Interfacing Analog and Digital Circuits

08. A weighted-resistor DAC derives its binary-weighted currents from binary-weighted resistors connected to the reference voltage supply.

09. An R-2R ladder DAC derives its binary weighted currents from a resistor ladder network that consists of resistors of two values only, one of which is twice the other. The R-2R ladder is more common than the weighted resistor DAC.

10.A DAC input code consisting of a 1 followed by all 0s repre-

sents an output of 12 FS, regardless of the number of bits in the DAC input. A code of 01 followed by all 0s represents an output of 14 FS. A code of 11 followed by all 0s is 34 FS.

11.The MC1408 DAC is an example of a monolithic (singlechip) DAC. Output current at pin 4 is a binary-weighted fraction of the reference current at pin 14:

=

digital code

Vref

Io

256

R14

12.If the output of an MC1408 DAC is buffered by an nonin-

verting op amp with a feedback resistance of RF, the output voltage is given by:

V

= I

R

= digital code

RF

V

a

o F

ref

256

R14

13.An 8-bit DAC can be used as a ramp generator by connecting an 8-bit binary counter to the digital inputs.

14.An MC1408 DAC can be configured for bipolar output by

connecting a pull-up resistor (R4) from the output (pin 4) to the reference voltage supply. Output is given by:

V

= I

R

− I R

=

digital code

RF

V

−

RF

V

a

o F

s F

ref

ref

256

R14

R4

15.A DAC is monotonic if every increase in binary input results in an increase in analog output.

16.DAC errors include: offset error (nonzero output for zero input code), gain error (output falling above or below FS 1LSB for maximum input code due to an incorrect slope), linearity error (deviation from straight-line approximation between codes), and differential nonlinearity (deviation of step sizes from ideal of one step per LSB).

17.DAC linearity error of greater than 12 LSB can result in a nonmonotonic output.

18.Several popular types of analog-to-digital converters (ADC) are flash or simultaneous, successive approximation, and dual slope or integrating.

19.AflashADCconsistsofavoltagedividerwiththesamenumber ofstepsasoutputcodes,asetofcomparators(oneforeveryoutput code), and a priority encoder.All comparators whose reference input is less than the analog input will fire, the priority encoder will detect the highest-value active comparator, and

generate the corresponding output code. A flash ADC is fast, but requires 2n comparators for an n-bit output code.

20.An ADC transfer characteristic is set up so that all codes are

1 LSB wide, except for the first and last codes. The code for

0 is 12 LSB wide and the maximum code is 112 LSB wide. This offset places the nominal analog value of the code in the center of the code’s range of analog input values.

21.A successive approximation ADC consists of a state machine called a successive approximation register (SAR) whose bits

can be set and cleared individually in a specific sequence, a digital-to-analog converter, and an analog comparator.

22.A successive approximation ADC sets each bit of the SAR in turn as an approximation of the required digital code. For each bit, the approximation is converted back to analog form and compared with the incoming analog value. If the converted value is less than the actual analog value, the bit remains set and the next bit is tried. If the converted value is greater than the actual analog input, the bit is cleared and the next bit is tried.

23.A dual slope ADC consists of an integrator, comparator, counter, and control logic. The integrator output changes with a slope of Vin/RC for a constant input. This ADC allows the integrator to charge for the time required for the counter to complete one full cycle (known time). At that time, the integrator input is switched to a reference voltage of opposite polarity. The reference voltage discharges the integrator at a known rate. The time required to do this is stored in the counter and represents the fraction of full scale analog voltage applied to the converter.

24.A sample and hold circuit may be required to hold the input value of an ADC constant for the conversion time of the ADC. It samples an analog signal at periodic intervals and holds the sampled value in a capacitor until the next sample is taken. A track and hold circuit performs a similar function, but allows the capacitor to charge and discharge along with the changing analog signal, holding its value only during the conversion time of the ADC.

25.In order to preserve the information in an analog signal, it must be sampled at a frequency of at least twice the maxi- mum-frequency component of the signal (fs fmax). This criterion is called the Nyquist sampling theorem.

26.If the Nyquist sampling theorem is violated, an alias frequency, or false low-frequency component, will be added to the digital representation of the analog signal.

27.Alias frequencies can be eliminated with an anti-aliasing filter, a low-pass filter used to pass only frequencies less than

2fs to the input of an ADC. This input frequency range automatically satisfies the Nyquist criterion at the ADC input.

28.An ADC0808 successive approximation ADC contains an 8-channel analog MUX and can be used as the basis for an 8-channel data acquisition system.

29.The conversion sequence for the ADC0808 is as follows:

a.an analog input channel is selected by setting the appropriate address on lines ADD C, ADD B, and

ADD A.

b.ALE and START are pulsed HIGH.

c.EOC (end-of-conversion) goes LOW no later than 8 clock cycles 2 s after START.

d.EOC goes HIGH when conversion is complete.

e.OE (output enable) is set HIGH to read converted output.

This sequence can be controlled by a CPLD-based state machine.

30.A data acquisition system based on an ADC0808 requires an octal latch for each analog channel, a state-machine controller, and a counter/decoder circuit to select the active analog channel and latch.

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