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C H A P T E R 13

Memory Devices and Systems

O U T L I N E

13.1Basic Memory Concepts

13.2Random Access Read/Write Memory (RAM)

13.3Read Only Memory (ROM)

13.4Sequential Memory: FIFO and LIFO

13.5Dynamic RAM Modules

13.6Memory Systems

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

Describe basic memory concepts of address and data.

Understand how latches and flip-flops act as simple memory devices and sketch simple memory systems based on these devices.

Distinguish between random access read/write memory (RAM) and read only memory (ROM).

Describe the uses of tristate logic in data bussing.

Sketch the circuits of static and dynamic RAM cells.

Sketch a block diagram of a static or dynamic RAM chip.

Describe various types of ROM cells and arrays: mask-programmed, UV erasable, and electrically erasable.

Use various types of ROM in simple applications, such as digital function generation.

Describe the basic configuration of flash memory.

Describe the basic configuration and operation of two types of sequential memory: first-in-first-out (FIFO) and last-in-first-out (LIFO).

Describe how dynamic RAM is configured into high capacity memory modules.

Sketch a basic memory system, consisting of several memory devices, an address and a data bus, and address decoding circuitry.

Represent the location of various memory device addresses on a system memory map.

Recognize and eliminate conditions leading to bus contention in a memory system.

Expand memory capacity by parallel bussing and CPLD-based decoding.

621


C H A P T E R 1 3 • Memory Devices and Systems

In recent years, memory has become one of the most important topics in digital electronics. This is tied closely to the increasing prominence of cheap and readily available microprocessor chips. The simplest memory is a device we are already familiar with: the D flip-flop. This device stores a single bit of information as long as necessary. This simple

concept is at the heart of all memory devices.

The other basic concept of memory is the organization of stored data. Bits are stored in locations specified by an “address,” a unique number which tells a digital system how to find data that have been previously stored. (By analogy, think of your street address: a unique way to find you and anyone you live with.)

Some memory can be written to and read from in random order; this is called random access read/write memory (RAM). Other memory can be read only: read only memory (ROM). Yet another type of memory, sequential memory, can be read or written only in a specific sequence. There are several variations on all these basic classes.

Memory devices are usually part of a larger system, including a microprocessor, peripheral devices, and a system of tristate busses. If dynamic RAM is used in such a system, it is often in a memory module of some type. The capacity of a single memory chip is usually less than the memory capacity of the microprocessor system in which it is used. In order to use the full system capacity, it is necessary to use a method of memory address decoding to select a particular RAM device for a specified portion of system memory.

13.1 Basic Memory Concepts

K E Y T E R M S

Memory A device for storing digital data in such a way that they can be recalled for later use in a digital system.

Data Binary digits (0s and 1s) that contain some kind of information. The digital contents of a memory device.

Address A number, represented by the binary states of a group of inputs or out-

puts, uniquely defining the location of data stored in a memory device.

Write Store data in a memory device.

Read Retrieve data from a memory device.

Byte A group of 8 bits.

Nibble Half a byte; 4 bits.

octal_latch.gdf 1x8mem.gdf

1x8mem.scf

Address and Data

A memory is a digital device or circuit that can store one or more bits of data. The sim-

component in a MAX PLUS II graphic file and configured as an 8-bit memory.

When the WRITEn line goes LOW, then HIGH, data at the DATA_IN are stored in the eight latches. Data are available at the DATA_OUT pins when READ is HIGH. Note that although the READ and WRITEn inputs are separate in this design, their functions would often be implemented as opposite logic levels of the same pin.

Figure 13.4 shows a simulation of the 8-bit memory. The LOW pulses on WRITEn write the data, shown as two hexadecimal digits on the DATA_IN line, into the latches. To read the values stored in the eight latches, we set READ HIGH. In between read states, all DATA_OUT lines are in the high-impedance state, indicated by the notation ZZ.


FIGURE 13.1

D-Type Latch

13.1 • Basic Memory Concepts

623

INPUT

OE

LATCH

D0

INPUT

D

Q

ENA

LATCH

D1

INPUT

D

Q

ENA

LATCH

D2

INPUT

D

Q

ENA

LATCH

D3

INPUT

D

Q

ENA

LATCH

D4

INPUT

D

Q

ENA

LATCH

D5

INPUT

D

Q

ENA

LATCH

D6

INPUT

D

Q

ENA

LATCH

D7

INPUT

D

Q

ENA

NOT

INPUT

Gn

FIGURE13.2

Octal Latch

TRI

OUTPUT

Q0

TRI

OUTPUT

Q1

TRI

OUTPUT

Q2

TRI

OUTPUT

Q3

TRI

OUTPUT

Q4

TRI

OUTPUT

Q5

TRI

OUTPUT

Q6

TRI

OUTPUT

Q7


624 C H A P T E R 1 3 • Memory Devices and Systems

FIGURE13.3

Octal Latch as 8-bit Memory

octal_latch

READ

INPUT

OE

OUTPUT

INPUT

D0

DATA_IN0

Q0

DATA_OUT0

DATA_IN1

INPUT

D1

OUTPUT

Q1

DATA_OUT1

DATA_IN2

INPUT

D2

OUTPUT

Q2

DATA_OUT2

DATA_IN3

INPUT

D3

Q3

OUTPUT

DATA_OUT3

INPUT

OUTPUT

DATA_IN4

D4

Q4

DATA_OUT4

DATA_IN5

INPUT

OUTPUT

D5

Q5

DATA_OUT5

DATA_IN6

INPUT

OUTPUT

D6

Q6

DATA_OUT6

INPUT

OUTPUT

DATA_IN7

INPUT

D7

Q7

DATA_OUT 7

WRITEn

Gn

FIGURE 13.4

Simulation of 8-bit Memory

4x8reg.gdf

Figure 13.5 shows an expanded version of the octal latch memory circuit. Four octal

ltch8lpm.vhd

latches are configured to make a 4 8-bit memory that can store and recall four separate

dcdr2to4.vhd

8-bit words. The octal latches are based on 8-bit latches instantiated in VHDL from the Al-

oct4tol.vhd

tera Library of Parameterized Modules (LPM). The remaining components of Figure 13.5

are behaviorally-designed VHDL components.

The 8-bit input data are applied to the inputs of all four octal latches simultaneously.

Data are written to a particular latch when a 2-bit address and a LOW on WRITEn cause

an output of a 2-line-to-4-line decoder to enable the selected latch. For example, when

ADDR[1..0] 01 AND WRITEn 0, decoder output Y1 goes HIGH, activating the

ENABLE input on latch 1. The values at DATA_IN[7..0] are transferred to latch 1 and

stored there when WRITEn goes HIGH.

The latch outputs are applied to the data inputs of an octal 4-to-1 multiplexer. Recall

that this circuit will direct one of four 8-bit inputs to an 8-bit output. The selected set of in-

puts correspond to the binary value at the MUX select inputs, which is the same as the ad-

dress applied to the decoder in the write phase. The MUX output is directed to the

DATA_OUT lines by an octal tristate bus driver, which is enabled by the READ line. To

1, we set the address to 01, as before, and make the READ line

the DATA_OUT lines are in the high-impedance state.

.scf

simulation of the 4 8-bit memory. The address inputs change in

a continuous binary sequence. For each address, a write pulse loads 8-bit data into the se-

lected latch. After all four latches have been loaded, the latches are read in a rotating

sequence. To read any new data from the memory, we would first have to write the new

data into one or more of the latch locations.