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626 C H A P T E R 1 3 • Memory Devices and Systems

FIGURE 13.6

Simulation of 4 8 Memory

RAM and ROM

K E Y T E R M S

Random access memory (RAM) A type of memory device where data can be accessed in any order, that is, randomly. The term usually refers to random access read/write memory.

Read only memory (ROM) A type of memory where data are permanently stored and can only be read, not written.

The memory circuit in Figure 13.5 is one type of random access memory, or RAM. Data can be stored in or retrieved from any address at any time. The data can be accessed randomly, without the need to follow a sequence of addresses, as would be necessary in a sequential storage device such as magnetic tape.

RAM has come to mean random access read/write memory, memory that can have its data changed by a write operation, as well as have its data read. The data in another type of memory, called read only memory, or ROM, can also be accessed randomly, although it cannot be changed, or at least not changed as easily as RAM; there is no write function; hence the name “read only.” Even though both types of memory are random access, we generally do not include ROM in this category.

Memory Capacity

K E Y T E R M S

b Bit.

B Byte.

K 1024 ( 210). Analogous to the metric prefix “k” (kilo-).

M 1,048,576 ( 220). Analogous to the metric prefix “M” (mega-).

The capacity of a memory device is specified by the address and data sizes. The circuit shown in Figure 13.5 has a capacity of 4 8 bits (“four-by-eight”). This tells us that the memory can store 32 bits, organized in groups of 8 bits at 4 different locations.

For large memories, with capacities of thousands or millions of bits, we use the shorthand designations K or M as prefixes for large binary numbers. The prefix K is analogous to, but not the same as, the metric prefix k (kilo). The metric kilo (lowercase k) indicates a multiplier of 103 1000; the binary prefix K (uppercase) indicates a multiplier of 210 1024. Thus, one kilobit (Kb) is 1024 bits.

particular control application) has a memory with a capacity of 64 Kb, organized as 8K 8. What is the total memory capacity of the system in bits? What is the memory capacity in bytes?

Solution The total number of bits in the system memory is:

8K 8 8 8 1K 64 Kb 64 1024 bits 65,536 bits The number of bytes in system memory is:

64 Kb 8 KB

8b/B

Usually, the range of numbers spanning 1K is expressed as the 1024 numbers from 010 to 102310 (00000000002 to 11111111112). This is the full range of numbers that can be expressed by 10 bits. In hexadecimal, the range of numbers spanning 1K is from 000H to 3FFH. The range of numbers in 1M is given as the full hexadecimal range of 20-bit num-

bers: 00000H to FFFFFH.

The range of numbers spanning 8K can be written in 13 bits (8 1K 23 210 213). The addresses in an 8K 8 memory range from 0000000000000 to 1111111111111, or 0000 to 1FFF in hexadecimal. Thus, a memory device that is organized as 8K 8 has 13 address lines and 8 data lines.

Figure 13.7 shows the address and data lines of an 8K 8 memory and a map of its contents. The addresses progress in binary order, but the contents of any location are the

FIGURE 13.7

Address and Data in an 8K 8 Memory

Control Signals

Two memory devices are shown in Figure 13.8. The device in Figure 13.8a is a 1K 4 random access read/write memory (RAM). Figure 13.8b shows 8K 8 erasable programmable read only memory (EPROM). The address lines are designated by A and the data lines by DQ. The dual notation DQ indicates that these lines are used for both input (D) and output (Q) data, using the conventional designations of D-type latches. The input and output data are prevented from interfering with one another by a pair of opposite-direction tristate buffers on each input/output pin. One buffer goes to a memory cell input; the other comes from the memory cell output. The tristate outputs on the devices in Figure 13.8 allow the outputs to be electrically isolated from a system data bus that would connect several such devices to a microprocessor.

FIGURE 13.8

Address, Data, and Control Signals

In addition to the address and data lines, most memory devices, including those in Figure 13.8, have one or more of the following control signal inputs. (Different manufacturers use different notation, so several alternate designations for each function are listed.)

E (or CE or CS). Enable (or Chip Enable or Chip Select). The memory is enabled when this line is pulled LOW. If this line is HIGH, the memory cannot be written to or read from.

W (or WE or R/W). Write (or Write Enable or Read/Write). This input is used to select the read or write function when data input and output are on the same lines. When HIGH, this line selects the read (output) function if the chip is selected. When LOW, the write (input) function is selected.

G (or OE). Gate (or Output Enable). Some memory chips have a separate control to enable their tristate output buffers. When this line is LOW, the output buffers are enabled and the memory can be read. If this line is HIGH, the output buffers are in the highimpedance state. The chip select performs this function in devices without output enable pins.

The electrical functions of these control signals are illustrated in Figure 13.9.

FIGURE 13.9

Memory Control Signals

630C H A P T E R 1 3 • Memory Devices and Systems

13.2Random Access Read/Write Memory (RAM)

K E Y T E R M S

Volatile A memory is volatile if its stored data are lost when electrical power is lost.

Static RAM A random access memory that can retain data indefinitely as long as electrical power is available to the chip.

Dynamic RAM A random access memory that cannot retain data for more than a few milliseconds without being “refreshed.”

RAM cell The smallest storage unit of a RAM, capable of storing 1 bit.

Random access read/write memory (RAM) is used for temporary storage of large blocks of data. An important characteristic of RAM is that it is volatile. It can retain its stored data only as long as power is applied to the memory. When power is lost, so are the data. There are two main RAM configurations: static (SRAM) and dynamic (DRAM).

Static RAM (SRAM) consists of arrays of memory cells that are essentially flip-flops. Data can be stored in a static RAM cell and left there indefinitely, as long as power is available to the RAM.

A dynamic RAM cell stores a bit as the charged or discharged state of a small capacitor. Since the capacitor can hold its charge for only a few milliseconds, the charge must be restored (“refreshed”) regularly. This makes a dynamic RAM (DRAM) system more complicated than SRAM, as it introduces a requirement for memory refresh circuitry.

DRAMs have the advantage of large memory capacity over SRAMs. At the time of this writing, the largest SRAMs have a capacity of about 4 Mb, whereas the largest DRAMs have a capacity of 256 Mb. DRAM modules, that is, groups of DRAM chips on a small circuit board, have capacities of up to 1 GB. These figures are constantly increasing and are never up to date for very long. (The most famous estimate of the growth rate of semiconductor memory capacity, Moore’s law, estimates that it doubles every 18 months. My casual observation is that this is accurate to within an order of magnitude.)

Static RAM Cells

The typical static RAM cell consists of at least two transistors that are cross-coupled in a flip-flop arrangement. Other parts of the cell include pull-up circuitry that can be active (transistor switches) or passive (resistors) and some decoding/switching logic. Figure 13.10 shows an SRAM cell in three technologies: bipolar, NMOS, and CMOS.

Each of these cells can store 1 bit of data, a 0 or a 1, as the state of one of the transistors in the cell. The data are available in true or complement form, as the BIT andBIT outputs of the flip-flop.

All types of SRAM cells operate in more or less the same way. We will analyze the operation of the NMOS cell (Figure 13.10b) and then compare it to the other types.

Transistors Q1 and Q2 are permanently biased ON, making them into pull-up resistors. Channel width and length are chosen to give a resistance of about 1 k . These NMOS load transistors are considered passive pull-ups, as they do not switch on and off.

A bit is stored as VDS3, the drain voltage of Q3 with respect to its source. If this voltage is HIGH, the gate of Q4 is HIGH with respect to its source and Q4 is biased ON. This completes a conduction path from the drain of Q4 to its source, making VDS4 logic LOW. This LOW is fed back to the gate of Q3, turning it OFF. There is no conduction path between the drain and source of Q3, so VDS3 VDD or logic HIGH. The cell is storing a 1.

This bit can be read by making the ROW SELECT line HIGH. This turns Q5 and Q6 ON, which puts the data onto the BIT and BIT lines where it can be read by other circuitry inside the RAM chip.

To change the cell contents to a 0, we make the BIT line LOW and the ROW SELECT line HIGH. The ROW SELECT line gives access to the cell by turning on Q5 and Q6, com-