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A P P E N D I X B

VHDL Language Reference

1.VHDL Basics

1.1.Valid Names

1.2.Comments

1.3.Entity and Architecture

1.4.Ports

1.5.Signals and Variables

1.6.Type

1.6.1.STD_LOGIC

1.6.2.Enumerated Type

1.7.Libraries and Packages

1.1Valid Names

A valid name in VHDL consists of a letter followed by any number of letters or numbers, without spaces. VHDL is not case sensitive. An underscore may be used within a name, but may not begin or end the name. Two consecutive underscores are not permitted.

EXAMPLES

Valid names:

decode4

just_in_time

What_4

Invalid names:

4decode

(begins with a digit)

in__time

(two consecutive underscores)

_What_4

(begins with underscore)

my design

(space inside name)

your_words?

(special character ? not allowed)

1.2 Comments

A comment is explanatory text that is ignored by the VHDL compiler. It is indicated by two consecutive hyphens.

EXAMPLE

—— This is a comment.

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1.3Entity and Architecture

All VHDL files require an entity declaration and an architecture body. The entity declaration indicates the input and output ports of the design. The architecture body details the internal relationship between inputs and outputs. The VHDL file name must be the same as the entity name.

Syntax:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY __entity_name IS

GENERIC(define parameters);

PORT(define inputs and outputs);

END __entity_name;

ARCHITECTURE a OF __entity_name IS

SIGNAL and COMPONENT declarations;

BEGIN statements;

END a;

EXAMPLES: ——Majority vote circuit (majority.vhd) LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY majority IS

PORT(

a, b, c: IN STD_LOGIC; y : OUT STD_LOGIC);

END majority;

ARCHITECTURE a OF majority IS

BEGIN

y <= (a and b) or (b and c) or (a and c); END a;

—— 2-line-to-4-line decoder with active-HIGH outputs (decoder.vhd) LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY decoder IS

PORT(

d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0));

END decoder;

ARCHITECTURE a OF decoder IS

BEGIN

WITH d SELECT

y <=

“0001” WHEN “00”,

“0010” WHEN “01”,

“0100” WHEN “10”,

“1000” WHEN “11”,

“0000” WHEN others;

END a;

A P P E N D I X B • VHDL Language Reference

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1.4

Ports

A port in VHDL is a connection from a VHDL design entity to the outside world. The

direction or directions in which a port may operate is called its mode. A VHDL port

may have one of four modes: IN (input only), OUT (output only), INOUT (bidirec-

tional), and BUFFER (output, with feedback from the output back into the design en-

tity). The mode of a port is declared in the port statement of an entity declaration or

component declaration.

EXAMPLES:

ENTITY mux IS

PORT(

s1, s0

: IN STD_LOGIC;

y0, y1, y2, y3 : OUT STD_LOGIC);

END mux;

ENTITY srg8 IS

PORT(

clock, reset

: IN

STD_LOGIC;

q

: BUFFER

STD_LOGIC_VECTOR (7 downto 0));

END srg8;

1.5

Signals and Variables

A signal is like an internal wire connecting two or more points inside an architecture body.

It is declared before the BEGIN statement of an architecture body and is global to the ar-

chitecture. Its value is assigned with the operator.

A variable is an piece of working memory, local to a specific process. It is declared be-

fore the BEGIN statement of a process and is assigned using the : operator.

EXAMPLE:

ARCHITECTURE a OF design4 IS

SIGNAL connect : STD_LOGIC_VECTOR ( 7 downto 0);

BEGIN

PROCESS check IS

VARIABLE count : INTEGER RANGE 0 TO 255;

BEGIN

IF (clock’EVENT and clock = ‘1’) THEN

count := count + 1;

—— Variable assignment statement

END IF;

END PROCESS;

connect <= a and b;

—— Signal assignment statement

END a;

1.6

Type

The type of a port, signal, or variable determines the values it can have. For example, a signal of type BIT can only have values ‘0’ and ‘1’. A signal of type INTEGER can have any

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integer value, up to the limits of the bit size of the particular computer system for which the VHDL compiler is designed. Some common types are:

Type

Values

How written

BIT

‘0’, ‘1’

Single quotes

STD_LOGIC

‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’,

Single quotes

(see Section 1.6.1)

‘L’, ‘H’, ‘-‘

INTEGER

Integer values

No quotes

BIT_VECTOR

Multiple instances of ‘0’ and ‘1’

Double quotes (e.g., “00101”)

STD_LOGIC_VECTOR

Multiple instances of ‘U’, ‘X’,

Double quotes (e.g., “11ZZ00”)

‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-‘

1.6.1STD_LOGIC

The STD_LOGIC (standard logic) type, also called IEEE Std.1164 Multi-Valued Logic, gives a broader range of output values than just ‘0’ and ‘1’. Any port, signal, or variable of type STD_LOGIC or STD_LOGIC_VECTOR can have any of the following values.

‘U’, —— Uninitialized

‘X’, —— Forcing

Unknown

‘0’, —— Forcing

0

‘1’, —— Forcing

1

‘Z’, —— High Impedance

‘W’, —— Weak

Unknown

‘L’, —— Weak

0

‘H’, —— Weak

1

‘-’, —— Don’t care

“Forcing” levels are deemed to be the equivalent of a gate output. “Weak” levels are specified by a pull-up or pull-down resistor. The ‘Z’ state is used as the high-impedance state of a tristate buffer.

The majority of applications can be handled by ‘X’, ‘0’, ‘1’, and ‘Z’ values.

To use STD_LOGIC in a VHDL file, you must include the following reference to the VHDL library called ieee and the std_logic_1164 package before the entity declaration.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

1.6.2Enumerated Type

An enumerated type is a user-defined type that lists all possible values for a port, signal, or variable. One use of an enumerated type is to list the states of a state machine.

EXAMPLE:

TYPE STATE_TYPE IS (idle, start, pulse, read);

SIGNAL state: STATE_TYPE;

1.7 Libraries and Packages

A library is a collection of previously compiled VHDL constructs that can be used in a design entity. A package is an uncompiled collection of VHDL constructs that can be used in multiple design entities. Library names must be included at the beginning of a VHDL file, before the entity declaration, to use certain types or functions. The most obvious is the library ieee, which in the package std_logic_1164, defines the STD_LOGIC (standard logic)

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