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2.5 Generate Statement

A generate statement is used to create multiple instances of a particular hardware structure. It relies on the value of one or more index variables to create the required number of repetitions.

Syntax:

__generate_label:

FOR __index_variable IN __range GENERATE __statement;

__statement; END GENERATE;

EXAMPLES: —— Instantiate four full adders adders:

FOR i IN 1 to 4 GENERATE

adder: full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum(i));

2.6 Process Statement

A process is a concurrent statement, but the statements inside the process are sequential. For example, a process can define a flip-flop, a separate component whose ports are affected concurrently, but the inside of the flip-flop acts sequentially. A process executes all statements inside it when there is a change of a signal in its sensitivity list. The process label is optional.

Syntax:

__process_label:

PROCESS (sensitivity list)

variable declarations

BEGIN

sequential statements

3.Sequential Structures

3.1.If Statement

3.1.1.Evaluating Clock Functions

3.2.Case Statement

A sequential structure in VHDL is one in which the order of statements affects the operation of the circuit. It can be used to implement combinational circuits, but is primarily used to implement sequential circuits such as latches, counters, shift registers, and state machines. Sequential statements must be contained within a process.

3.1 If Statement

An IF statement executes one or more statements if a Boolean condition is satisfied.

Syntax:

IF __expression THEN __statement; __statement;

ELSIF __expression THEN __statement; __statement;

ELSE __statement; __statement;

END IF;

EXAMPLE: PROCESS (reset, load, clock)

VARIABLE count INTEGER RANGE 0 TO 255;

BEGIN

IF (reset = ‘0’) THEN q <= 0;

ELSIF (reset = ‘1’ and load = ‘0’) THEN q <= p;

ELSIF (clock’EVENT and clock = ‘1’) THEN count := count + 1;

q <= count; END IF;

700 A P P E N D I X B • VHDL Language Reference

3.1.1Evaluating Clock Functions

As implied in previous examples, the state of a system clock can be checked with an IF statement using the predefined attribute called EVENT. The clause clock’EVENT (“clock tick EVENT”) is true if there has been activity on the signal called clock. Thus (clock’EVENT and clock ‘1’) is true just after a positive edge on clock.

3.2 Case Statement

A case statement is used to execute one of several sets of statements, based on the evaluation of a signal.

Syntax:

CASE __expression IS

WHEN __constant_value => __statement; __statement;

WHEN __constant_value => __statement; __statement;

WHEN OTHERS => __statement; __statement;

END CASE;

EXAMPLES: —— Case evaluates 2-bit value of s and assigns

——4-bit values of x and y accordingly

——Default case (others) required if using STD_LOGIC CASE s IS

WHEN “00” =>

y <= “0001”; x <= “1110”;

WHEN “01” =>

y <= “0010”; x <= “1101”;

WHEN “10” =>

y <= “0100”; x <= “1011”;

WHEN “11” =>

y <= “1000”; x <= “0111”;

WHEN others => y <= “0000”;

x <= “1111”;

END CASE;

——This case evaluates the state variable “sequence”

——that can have two possible values: “start” and “continue”

——Values of out1 and out2 are also assigned for each case. CASE sequence IS

WHEN start =>

IF in1 = ‘1’ THEN

sequence <= start; out1 <= ‘0’;

out2 <= ‘0’; ELSE

sequence <= continue; out1 <= ‘1’;

out2 <= ‘0’;

A P P E N D I X C

Manufacturers’ Data Sheets

Data Sheet List