Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
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300 C H A P T E R 7 • Introduction to Sequential Logic
Figure 7.40 shows a circuit that acts as a simplified positive edge detector. Edge detection depends on the fact that a gate output does not switch immediately when its input switches. There is a delay of about 3 to 10 ns from input change to output change, called propagation delay.
FIGURE 7.40
Positive Edge Detector
When input x, shown in the timing diagram of Figure 7.40, goes from LOW to HIGH, the inverter output, x, goes from HIGH to LOW after a short delay. This delay causes both x and x to be HIGH for a short time, producing a high-going pulse at the circuit output immediately following the positive edge at x.
When x returns to LOW, x goes HIGH after a delay. However, there is no time in this sequence when both AND inputs are HIGH. Therefore, the circuit output stays LOW after the negative edge of the input waveform.
Figure 7.41 shows how the D flip-flop circuit operates. When D 0 and the edge detector senses a positive edge at the CLK input, the output of the lower NAND gate steers a low-going pulse to the RESET input of the latch, thus storing a 0 at Q. When D 1, the upper NAND gate is enabled. The edge detector sends a high-going pulse to the upper steering gate, which transmits a low-going SET pulse to the output latch. This action stores a 1 at Q.
FIGURE 7.41
Operation of a D Flip-Flop
7.4 • |
Edge-Triggered D Flip-Flops |
301 |
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EXAMPLE 7.6 |
Figure 7.42 shows a MAX PLUS II Graphic Design File with a D latch and a D flip- |
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flop connected to the same data input and clock. Create a MAX PLUS II simulation that |
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illustrates the difference between the latch (level-sensitive enable) and the flip-flop (edge- |
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triggered clock). |
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LATCH |
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INPUT |
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D |
D |
OUTPUT |
Q_latch |
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INPUT |
Q |
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CLK |
ENA |
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DFF
PRN |
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D |
OUTPUT |
Q_flip_flop |
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Q |
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CLRN |
FIGURE 7.42
D Latch and D Flip-Flop
SOLUTION The simulation, shown in Figure 7.43, has a 200 ns grid. Several points on the waveform indicate the similarities and differences between the latch and flip-flop operation.
FIGURE 7.43
Simulation showing the Difference between D Latch and D Flip Flop
latch_ff.gdf latch_ff.scf
2.D goes LOW at 2 s. Both Q outputs go LOW at 2.8 s since the positive edge of the CLK and its HIGH level occur at the same time.
3.The D input goes HIGH at 4.4 s, in the middle of a CLK pulse. Since the CLK line is HIGH, Q_ latch changes immediately. Q_ flip_ flop does not change until the next positive edge, at 6 s.
4.D goes LOW at 7.8 s. Q_latch also changes at this time, since CLK is HIGH. Q_ flip_ flop changes on the next positive edge, at 9.2 s.
302 C H A P T E R 7 • Introduction to Sequential Logic
Note that the latch output is in an unknown state until the first CLK pulse, whereas the |
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flip-flop output is LOW, even before the first CLK pulse. This is because Altera CPLDs |
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have power-on reset circuitry that ensures that flip-flop outputs in a CPLD are LOW im- |
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mediately after power is applied to the device. The MAX PLUS II simulator accounts for |
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this condition. |
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EXAMPLE 7.7 |
Two positive edge-triggered D flip-flops are connected as shown in Figure 7.44a. Inputs D0 |
and CLK are shown in the timing diagram. Complete the timing diagram by drawing the |
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waveforms for Q0 and Q1, assuming that both flip-flops are initially reset. |
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FIGURE 7.44 |
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Example 7.7 |
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Circuit and Timing Diagram |
SOLUTION Figure 7.44b shows the output waveforms. Q0 follows D0 at each point where the clock input has a positive edge. One result of this is that the HIGH pulse on D0 between clock pulses 5 and 6 is ignored, since D0 0 on positive edges 5 and 6.
Since D1 Q0 and Q1 follows D1, the waveform at Q1 is the same as at Q0, but delayed by one clock cycle. If Q0 changes due to CLK, we assume that the value of D1 is the same as Q0 just before the clock pulse. This is because delays within the circuitry of the flip-flops ensure that their outputs will not change for several nanoseconds after an applied clock pulse. Therefore, the level at D1 remains constant long enough for it to be clocked into the second flip-flop.
The data entering the circuit at D0 are moved, or shifted, from one flip-flop to the next. This type of data movement, called “serial shifting,” is frequently used in data communi-
cation and digital arithmetic circuits. |
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SECTION 7.4 REVIEW PROBLEM
7.4Which part of a D flip-flop accounts for the difference in operation between a D flipflop and a D latch? How does it work?
304 C H A P T E R 7 • Introduction to Sequential Logic
FIGURE 7.47 |
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Toggle Action of a JK Flip-Flop |
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EXAMPLE 7.8 |
The J, K, and CLK inputs of a negative edge-triggered JK flip-flop are as shown in the tim- |
ing diagram in Figure 7.48. Complete the timing diagram by drawing the waveforms for Q |
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and Q. Indicate which function (no change, set, reset, or toggle) is performed at each clock |
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pulse. The flip-flop is initially reset. |
FIGURE 7.48 |
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Example 7.8 |
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Timing Diagram (Negative-Edge-Triggered JK Flip-Flop) |
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SOLUTION The completed timing diagram is shown in Figure 7.48. The outputs change |
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only on the negative edges of the CLK waveform. Note that the same output sometimes re- |
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sults from different inputs. For example, the function at clock pulse 4 is reset and the func- |
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tion at pulses 5 and 6 is no change, but the Q waveform is LOW in each case. |
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EXAMPLE 7.9 |
The toggle function of a JK flip-flop is often used to generate a desired output sequence |
from a series of flip-flops. The circuit shown in Figure 7.49 is configured so that all flip- |
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flops are permanently in toggle mode. |
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Assume that all flip-flops are initially reset. Draw a timing diagram showing the CLK, |
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Q0, Q1, and Q2 waveforms when eight clock pulses are applied. Make a table showing each |