Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

Figure 7.53 shows the circuit of a 3-bit synchronous counter. Unlike the circuit in Figure 7.49, the flip-flops in this circuit are clocked from a common source. Therefore, flip-flop delays do not add up through the circuit, and all the outputs change at the same time. Figure 7.54 shows a simulation of the circuit of Figure 7.53. Note that the outputs progress in a binary sequence, and there are no intermediate states.

FIGURE 7.54

Simulation of a 3-bit Synchronous Counter

The circuit works as follows:

1.Flip-flop 0 is configured for toggle mode (J0K0 11). Since the flip-flops in Figure 7.53 are positive edge-triggered, Q0 toggles on each positive clock edge.

2.Q0 is connected to inputs J1 and K1. Since these inputs are tied together, only two states are possible: no change (JK 00) or toggle (JK 11). If Q0 1, Q1 toggles. Otherwise, it does not change. This results in a Q1 waveform that toggles at half the rate of Q0.

3.J2 and K2 are both tied to the output of an AND gate. The AND gate output is HIGH if both Q1 and Q0 are HIGH. This makes Q2 toggle, since J2K2 11. In all other cases, there is no change on Q2. The result of this is that Q2 toggles every fourth clock pulse, the only times when Q1 and Q0 are both HIGH.

Asynchronous Inputs (Preset and Clear)

K E Y T E R M S

Synchronous inputs The inputs of a flip-flop that do not affect the flip-flop’s Q outputs unless a clock pulse is applied. Examples include D, J, and K inputs.

Asynchronous inputs The inputs of a flip-flop that change the flip-flop’s Q outputs immediately, without waiting for a pulse at the CLK input. Examples include preset and clear inputs.

Preset An asynchronous set function.

Clear An asynchronous reset function.

The D, J, and K inputs of the flip-flops examined so far are called synchronous inputs. This is because any effect they have on the flip-flop outputs is synchronized to the CLK input.

Another class of input is also provided on many flip-flops. These inputs, called asynchronous inputs, do not need to wait for a clock pulse to make a change at the output. The two functions usually provided are preset, an asynchronous set function, and clear, an

asynchronous reset function. These functions are generally active LOW, and are abbreviated PRE and CLR.

Figure 7.55 shows a modification to the JK flip-flop of Figure 7.46. The PRE and CLR inputs have direct access to the latch gates of the flip-flop and thus are not affected by the

308 C H A P T E R 7 • Introduction to Sequential Logic

FIGURE 7.55

PRE and CLR Inputs

FIGURE 7.56

Example 7.10

Waveforms

SOLUTION The Q waveform is shown in Figure 7.56. The asynchronous inputs cause an immediate change in Q, whereas the synchronous inputs must wait for the next negative clock edge. If asynchronous and synchronous inputs are simultaneously active, the asynchronous inputs have priority. This occurs in two places: pulse 3 (K, PRE) and pulse 10

(J, CLR).

The diagram shows the synchronous functions (no change, reset, set, and toggle) at each clock pulse and the asynchronous functions (preset and clear) at the corresponding transi-

tion points.

The function table of a negative edge-triggered JK flip-flop with preset and clear functions is shown in Table 7.9.

310 C H A P T E R 7 • Introduction to Sequential Logic

Figure 7.58 shows a set of simulation waveforms that illustrate the asynchronous clear function. When RESET is HIGH, the count proceeds normally. The positive clock edge at 440 ns drives the counter to state 011. The reset pulse at 460 ns sets the counter to 000 as soon as it goes LOW. On the next clock edge, the count proceeds from 000.

FIGURE 7.58

Simulation of Synchronous Counter with Asynchronous Reset

The function that sets all flip-flops in a circuit to a known initial state is sometimes called Master Reset.

SECTION 7.5 REVIEW PROBLEM

7.5What is the main difference between synchronous and asynchronous circuits, such as the two counters in Figures 7.49 and 7.53? What disadvantage is there to an asynchronous circuit?

7.6Edge-Triggered T Flip-Flops

K E Y T E R M

T (toggle) flip-flop A flip-flop whose output toggles between HIGH and LOW

states on each applied clock pulse when a synchronous input, called T, is active.

In the section on the JK flip-flop, we saw how that device can be set to toggle between HIGH and LOW output states. Other types of flip-flops can perform this function, as well. For example, Figure 7.59 shows a D flip-flop configured for toggle operation. Since Q follows D and D Q in this circuit, then the flip-flop output must change to its opposite state with each clock pulse. Figure 7.60 shows a MAX PLUS II simulation of this circuit.

FIGURE 7.59

D Flip-Flop Configured for Toggle Function