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336 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.6

4-to-1 Multiplexer Circuits

In order to examine the general principle of fuse programming, let us develop the programmed logic diagram for a common combinational circuit: a 4-to-1 multiplexer. (After developing the fuse maps for several examples, we will not refer to this technique again.)

This circuit, shown in Figure 8.6a, directs one of four input logic signals, D0 to D3, to output Y, depending on the state of two select inputs S0 and S1. The circuit works on the enable/inhibit principle; each AND gate is enabled by a different combination of S1 S0. The binary state of the select inputs is the same as the decimal subscript of the selected data input. For instance, S1 S0 10 selects data input D2; the AND gate corresponding to D2 is enabled and the other three ANDs are inhibited.

The logic equation for output Y is given by:

Y D0 S1 S0 D1 S1 S0 D2 S1 S0 D3 S1 S0

Since the outputs of the PAL16L8 are active LOW, as illustrated in Figure 8.6b, we should rewrite the equation as follows:

Y D0 S1 S0 D1 S1 S0 D2 S1 S0 D3 S1 S0

The D inputs must be complemented to reverse the effect of the active-LOW output. The output is enabled when the EN input is HIGH. Figure 8.7 shows the PAL16L8A logic diagram with fuses for the multiplexer application.

8.3 PAL Outputs With Programmable Polarity

The multiplexer application developed in the previous section uses a PAL device whose output is always fixed at the active-LOW polarity. This fixed polarity is suitable for most applications, but Boolean functions that would normally have active-HIGH outputs must be implemented in DeMorgan equivalent form, which is not always very straightforward.

Some applications require both active-HIGH and active-LOW outputs. In such cases, it is useful to have a device whose output polarity is fuse programmable.

Figure 8.8 shows the logic diagram of a PAL20P8 PAL device. This device is the same as a PAL16L8, except that there are four more dedicated inputs, and the polarity of each output is programmable. The Exclusive OR gate on each output is programmed to act as either an inverter or a buffer. When its associated fuse is intact, the XOR input is grounded and passes the output of its related SOP network in true form. When combined with the output inverter, this produces an active-LOW output. When the polarity fuse is blown, the fused XOR input floats to the HIGH state, inverting the SOP output; the output pin becomes active HIGH.

FIGURE 8.7

Programmed Logic Diagram for a 4-to-1 Multiplexer

The polarity fuses are given numbers higher than those of the main fuse array. In this case, the product line fuses are numbered 0000 to 2559 and the output polarity fuses are numbered 2560 to 2567.

Figure 8.9 illustrates the selection of output polarity. Two Boolean functions, F1 and F2, are programmed into the fuse array, with outputs at pins (17) and (15), respectively. The equations are:

F1 A B A B

F2 A B A B

338 C H A P T E R 8 • Introduction to Programmable Logic Architectures

FIGURE 8.8

PAL20P8 Logic Diagram

We could, if we chose, rewrite F2 to show the output as active LOW:

F2 A B A B

The portion of the PAL20P8 logic diagram shown in Figure 8.9 represents the fuses required to program F1 and F2. Pins (14) and (16) supply inputs A and B to the matrix. The ENABLE lines of the tristate output buffers float HIGH, since all fuses are blown on the corresponding product lines, thus permanently enabling the output buffers.

The fuses numbered 2565 and 2567 select the polarity at pins (15) and (17). Fuse 2565 is blown. The fused input to the corresponding XOR gate floats HIGH, thus making the gate into an inverter. Combined with the tristate buffer, this makes pin (17) active HIGH.

Fuse 2567 is intact. This grounds the input to the corresponding XOR gate, making the gate into a noninverting buffer. Combined with the tristate output buffer, this makes pin (15) active LOW.

FIGURE 8.9

PAL Outputs With Programmable Polarity

How would the implementation of these logic functions differ if only active-LOW outputs were available, as in a PAL16L8?

SOLUTION The PAL20P8 has 14 dedicated inputs, 2 dedicated outputs, and 6 lines that can be used as inputs or outputs. Our functions need 13 input variables and 7 output variables. We will use six I/O pins (pins (16) through (21)) and one dedicated output (pin (15)) for the output variables.

8.4 PAL Devices With Registered Outputs

K E Y T E R M S

Register A digital circuit such as a flip-flop or array of flip-flops that stores one or more bits of digital information.

Registered output An output of a programmable array logic (PAL) device having a flip-flop (usually D-type) that stores the output state.

Flip-flops are generally found in programmable logic devices as registered outputs. A register is one or more flip-flops used to store data. Registered outputs in programmable array logic (PAL) devices can be used for the same functions as individual flip-flops.

Figure 8.11 shows the logic diagram of a PAL device with eight registered outputs: a PAL16R8. The fuse matrix is identical to that of a PAL16L8 device; the differences

FIGURE 8.11

PAL16R8 Logic Diagram

342 C H A P T E R 8 • Introduction to Programmable Logic Architectures

This operation is usually performed by serially shifting the data the required number of places and feeding back the last output to the first input of a serial shift register.

Rotation can also be accomplished by a parallel transfer operation. We can load the bits of the input into four D flip-flops in the order determined by two select inputs, S1 and S0. Assume that the binary number S1 S0 is the same as the rotation number in Figure 8.12. Table 8.1 summarizes the contents of the circuit after one clock pulse is applied.

Table 8.1 Rotation to the Right by a Selectable Number of Bits

Sketch a circuit, using gates and flip-flops, that can accomplish this rotation as a parallel transfer function. Briefly explain its operation.

Write the Boolean expression(s) for the circuit.

Show how the circuit can be implemented by a PAL16R4 device by drawing fuses on its logic diagram.

SOLUTION Figure 8.13 shows a parallel transfer circuit (barrel shifter) that will perform the specified rotation. The circuit works by enabling one AND gate in each group of four for each combination of S1 and S0. For example, when S1 S0 00, the rotation is 0 and the leftmost AND gate of each group is enabled, transferring the parallel data into the flip-flops so that DA A, DB B, DC C, and DD D. After one clock pulse, QA

QB QC QD ABCD.