Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

FIGURE 7.82

Problem 7.24

Waveforms

COMPONENT DFF

END COMPONENT;

Disregard the clrn (active-LOW clear) and prn (ac- tive-LOW preset) ports for this problem. (Hint: you may have to use a component declaration in your file that only declares the ports d, clk, and q.)

Problems 323

7.27Write a VHDL file that creates a 12-bit D flip-flop, using the LPM component lpm_ff. (This component is instantiated as a D flip-flop by default. The required LPM component port names are: data, clock, and q.)

Section 7.5 Edge-Triggered JK Flip-Flops

7.28The waveforms in Figure 7.83 are applied to a negative edge-triggered JK flip-flop. Complete the timing diagram by drawing the Q waveform.

7.29Repeat Problem 7.28 for the waveforms in Figure 7.84.

7.30Given the inputs x, y, and z to the circuit in Figure 7.85, draw the waveform for output Q.

FIGURE 7.83

Problem 7.28

Waveforms

FIGURE 7.84

Problem 7.29

Waveforms

FIGURE 7.85

Problem 7.30 Inputs to Circuit

CLK

J

K

Q

CLK

J

K

Q

CLK

x

y

z

Q

7.31Assume that all flip-flops in Figure 7.86 are initially set.

Draw a timing diagram showing the CLK, Q0, Q1, and Q2 waveforms when eight clock pulses are applied. Make a

table showing each combination of Q2, Q1, and Q0. What pattern do the outputs form over the period shown on the timing diagram?

7.32Refer to the JK flip-flop circuit in Figure 7.87. Is the circuit synchronous or asynchronous? Explain your answer.

7.33Assume all flip-flops in the circuit in Figure 7.87 are reset. Analyze the operation of the circuit when six-

teen clock pulses are applied by making a table showing the sequence of states of Q3Q2Q1Q0, beginning at 0000.

7.34Draw a timing diagram showing the sequence of states from the table derived in Problem 7.33.

7.35The waveforms shown in Figure 7.88 are applied to a negative edge-triggered JK flip-flop. The flip-flop’s Preset and Clear inputs are active LOW. Complete the timing diagram by drawing the output waveforms.

7.36Repeat Problem 7.35 for the waveforms in Figure 7.89.

7.37Create a MAX PLUS II Graphic Design File for the synchronous circuit in Figure 7.87. Modify the circuit to add an asynchronous Master Reset function. Create a simulation file to verify the circuit operation.

7.38Modify the gdf created in Problem 7.37 to include a Master Reset function and an asynchronous preset function that will set the state of the circuit to Q3Q2Q1Q0 1010 when activated. Create a simulation file to verify the circuit operation.

7.39The term asynchronous is sometimes used to refer to the configuration of a circuit (e.g., a 3-bit asynchronous counter) and sometimes to a type of input to a device (e.g., an asynchronous clear input). Briefly explain how these two usages are similar and how they are different.

7.40Write a VHDL file for a 12-bit D flip-flop that uses MAX PLUS II DFF primitives, similar to that in Problem 7.26. Include active-LOW asynchronous clear (CLRN)

CLK

T

Q

FIGURE 7.90

Problem 7.42

Timing Diagram

and preset (PRN) inputs. Create a simulation file to verify the operation of your design.

7.41Write a VHDL file for a 12-bit D flip-flop with asynchronous preset and clear, using the LPM component lpm_ff, similar to that in Problem 7.27. Required ports: data, clock, aclr (asynchronous clear), aset (asynchronous set), and q. Ports aset and aclr are active-HIGH. Add two signals to the VHDL design to make them active-LOW. Create a simulation file to verify the operation of your design.

Section 7.6 Edge-Triggered T Flip-Flops

7.42The T and CLK waveforms for a positive-edge triggered T flip-flop is shown in Figure 7.90. Complete the timing diagram.

7.43The T and CLK waveforms for a positive-edge triggered T flip-flop is shown in Figure 7.91. Complete the timing diagram.

7.44Refer to the synchronous circuit in Figure 7.87. Create a MAX PLUS II Graphic Design File for a circuit with the same function, using T flip-flops rather than JK flipflops. Include an asynchronous reset input in the circuit. Create a simulation file to test the operation of the circuit.

7.45Write a VHDL file that implements the circuit you drew in Problem 7.44. Use TFF primitives in the design.

Section 7.7 Timing Parameters

7.46Use a TTL or high-speed CMOS data sheet, as appropriate, to look up the setup and hold times of the following devices:

a.74LS74A

b.74HC76

c.74LS76A

d.74LS107A

e.74ALS112A

f.74HC112

7.47Draw a timing diagram showing the setup and hold times for a 74LS76A flip-flop.

7.48Draw timing diagrams (to scale) showing setup and hold times, minimum CLK and CLR pulse widths, recovery time, and propagation delay times from CLK and CLR for both 74LS107A and 74HC107 flip-flops.

7.49Write names and values of the JK flip-flop timing parameters illustrated in Figure 7.92.

FIGURE 7.92

Problem 7.49

Timing Parameters

7.50Repeat Problem 7.49 for the timing diagram in Figure 7.93.

FIGURE 7.93

Problem 7.50

Timing Diagram

Section 7.1

7.1 The latch resets (i.e., Q goes LOW) upon receiving the first reset pulse. At that point, the latch is already reset, so further pulses are ignored.

Section 7.2

7.2 The NOR latch has active-HIGH inputs. If you make both inputs HIGH, you are attempting to set and reset the latch at the same time, which is a contradictory action. A NAND latch has active-LOW inputs. Therefore, if both inputs are HIGH, neither the set nor reset function activates and there is no change on the latch output.

Section 7.3

7.3

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY altera;

USE altera.maxplus2.ALL;

ENTITY lch16prm IS

ARCHITECTURE a OF lch16prm IS

BEGIN

—— Instantiate a latch from a MAX PLUS II primitive latch4:

FOR i IN 15 downto 0 GENERATE latch_primitive: latch

PORT MAP (d d in (i),

ena enable, q q out (i) ); END GENERATE;

END a;

Section 7.4

7.4 The edge detector circuit in the clock circuit accounts for the operational difference between a D flip-flop and a D latch. It works by using the difference in internal delay times between the gates that comprise the flip-flop’s clock input circuit.

Section 7.5

7.5 The flip-flops in asynchronous circuits are not all clocked at the same time; they are asynchronous with respect to the system clock. The flip-flops in a synchronous circuit have a common clock connection, which makes them synchronous to the system clock. The disadvantage to asynchronous circuits is that the internal delays of flip-flops can lead to unwanted intermediate states, since the flip-flops do not all change at the same time.