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Table 8.2 Truth Table for a 2-bit Equality Comparator

A1

A0

B1

B0

Decimal

AEQB

0

0

0

0

0

1

0

0

0

1

1

0

0

0

1

0

2

0

0

0

1

1

3

0

0

1

0

0

4

0

0

1

0

1

5

1

0

1

1

0

6

0

0

1

1

1

7

0

1

0

0

0

8

0

1

0

0

1

9

0

1

0

1

0

10

1

1

0

1

1

11

0

1

1

0

0

12

0

1

1

0

1

13

0

1

1

1

0

14

0

1

1

1

1

15

1

8.7 • FLEX10K CPLD

355

LUT

A1

A0B1 AEQB

B0

a. 2-bit comparator look-up table

Q0

AEQB

D

Q

ADDR0

Q1

D

Q

ADDR1

Storage

Elements

Q15

D

Q

ADDR15

Address decoder

A1

ADDR0

A0

ADDR1

B1

B0

ADDR15

b. Stuctural concept of a look-up table

FIGURE 8.22

Look-up Table

Figure 8.22 shows the structural concept of a 4-bit look-up table circuit. An array of 16 flip-flops (Q0 through Q15) contain data for all possible combinations of A1A0B1B0, one flip-flop per combination. The LUT inputs A1A0B1B0 are decoded by an internal address decoder. Each decoder output activates a tristate buffer that passes or blocks the output of one flip-flop. The active buffer passes the contents of the flip-flop to AEQB; all other buffers are in the high-impedance state, blocking the data from the other flip-flops.

The contents of the flip-flops are loaded when the look-up table is configured (programmed) with the required function. After that the flip-flops retain their information until they are reconfigured. For our comparator example, flip-flops 0, 5, 10, and 15 are all set (Q 1). All other flip-flops are reset (Q 0). Examine Table 8.2 to confirm that this is true.

The 16-bit storage element in Figure 8.22, combined with switching to choose a combinational or registered output and to interconnect with other parts of the chip, is called a logic element (LE). A logic element performs a function similar to that of a macrocell in SOP-type PLDs.

Figure 8.23 shows the structure of a logic element in an Altera FLEX10K CPLD. In addition to the LUT, the LE has circuitry to select various control functions, such as clock and reset, a flip-flop for registered output, some expansion circuitry (cascade and carry), and interconnections to local and global busses.

The cascade chain circuit, shown in Figure 8.24 allows the user to program Boolean functions with more than four inputs, thus requiring more than one LUT. The

356

C H A P T E R

8

• Introduction to Programmable Logic Architectures

Carry-In

Cascade-In

Register Bypass

Programmable

Register

DATA1

DATA2

Look-Up

Carry

Cascade

to FastTrack

Table

PRN

DATA3

(LUT)

Chain

Chain

D

Q

Interconnect

DATA4

ENA

CLRN

LABCTRL1

Clear/

to LAB local

LABCTRL2

Preset

Interconnect

Logic

Chip-Wide

Reset

Clock

Select

LABCTRL3

LABCTRL4

Carry-Out

Cascade-Out

FIGURE 8.23

FLEX10K Logic Element (Courtesy of Altera)

AND Cascade Chain

OR Cascade Chain

d[3..0]

d[3..0]

LUT

LE1

LUT

LE1

d[7..4]

LUT

d[7..4]

LUT

LE2

LE2

d[(4n-1)..(4n-4)]

d[(4n-1)..(4n-4)]

LUT

LUT

LEn

LEn

FIGURE 8.24

Cascade Chain Operation (Courtesy of Altera)

FIGURE 8.25

Carry Chain Operation

(n-bit Full Adder)

(Courtesy of Altera)

8.7 • FLEX10K CPLD

357

Carry-In

a1

LUT

Register

s1

b1

Carry

Chain

LE1

a2

LUT

Register

s2

b2

Carry

Chain

LE2

an

LUT

Register

sn

bn

Carry

Chain

LEn

LUT

Register

Carry-Out

Carry

Chain

LEn + 1

cascade chain can be ANDor OR-type, depending on what DeMorgan equivalent form is most appropriate.

The carry chain, shown in Figure 8.25 allows for efficient fast-carry implementation of adders, comparators, and other circuits that depend on the combination of low-order bits to define high-order functions (i.e., circuits whose inputs become wider with higherorder bits). Figure 8.25 shows the carry chain as implemented by an n-bit adder.

A Logic Array Block (LAB), shown in Figure 8.26, consists of eight logic elements and a local interconnect. The LAB is connected to the rest of the device by a series of row and column interconnects, which Altera calls a FastTrack Interconnect. Figure 8.27 shows the overall structure of a FLEX10K device, with several LABs and a number of

358 C H A P T E R 8 • Introduction to Programmable Logic Architectures

Dedicated Inputs and

Global Signals

Row Interconnect

6

16

4

LAB Local

4

Carry-In and

Interconnect

Cascade-In

2

8

24

4

LAB Control

4

LE1

Signals

4

LE2

4

LE3

16

8

4

LE4

4

LE5

4

LE6

4

LE7

4

LE8

8

2

Carry-Out and

Cascade-Out

FIGURE 8.26

FLEX10K LAB (Courtesy of Altera)

Column-to-Row

Interconnect

Column

Interconnect

Embedded Array Blocks (EABs). An EAB is an array of 2048 storage elements that can be used to efficiently implement complex logic functions.

The FLEX10K device found on the Altera UP-1 board—the EPF10K20RC240-4— has an array of 6 rows by 24 columns of LABs, which gives a total of 144 LABs ( 8 144 1152 logic elements). The device also has 6 EABs (6 2048 12288 bits of EAB storage). Note that one EAB has significantly more storage capacity than all LABs combined.

The FLEX10K series of CPLDs (and LUT-based devices generally) are based on static random access memory (SRAM) technology. The advantage of this configuration is that it can be manufactured with a very high density of storage cells and it programs quickly compared to an EEPROM-based SOP device. The disadvantage is that SRAM cells are volatile; that is, they do not retain their data when power is removed from the circuit. An SRAM-based device must be reconfigured every time it is powered up.

1.Programmable logic devices (PLDs) are configured in two basic architectures: sum-of-products (SOP), which usually consist of a se-

Embedded Array Block (EAB)

I/O Element

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

(IOE)

IOE

IOE

Column

Interconnect

EAB

IOE

IOE

Row

EAB

Interconnect

Logic

Array

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

IOE

Embedded Array

FIGURE 8.27

FLEX10K Device Block Diagram (Courtesy of Altera)

Summary 359

IOE

IOE

Logic Array

Logic Array

Block (LAB)

IOE

IOE

Logic Element (LE)

Local Interconnect

S U M M A R Y

ries of programmable AND/OR circuits, and look-up table (LUT), that stores the truth table of a Boolean function in a small memory.

2.Programmable array logic (PAL) is an SOP-type architecture in which there are a series of programmable AND gates that have a fixed connection to an OR-gate output.

3.Connections from PLD inputs to PAL AND arrays were historically made by leaving intact selected fuses in a crosspoint fuse array. In modern PLDs, these connections are made by programming EEPROM (electrically erasable programmable read only memory) cells.

4.An AND-gate input in a PAL array is called a product line.

5.A PAL16L8 PLD is an SOP device with up to 16 inputs and up to 8 outputs. There are 10 dedicated inputs, 2 dedicated outputs, and 6 pins that can be configured as input or output. All outputs in the PAL16L8 are active-LOW.

6.A PAL is programmed by a computer and programming hardware that uses a JEDEC file as a template for determin-

ing which fuses to blow and which to leave intact.

7.Some PAL devices have programmable-polarity outputs. This is achieved with an XOR gate that has a programmable cell or fuse on one input to switch the output between inverting and noninverting levels.

8.A registered PLD output consists of a flip-flop (usually D-type) on the output of an SOP matrix.

9.A PAL part number indicates the number of registered outputs (e.g., a PAL16R8 has eight registered outputs).

10.Early-version standard PALs are limited in that they are one-time programmable (OTP), their outputs are permanently configured as combinational or registered, and they cannot be programmed in-system. Later-version PALs (e.g., PAL16CE16V8 Universal PAL) and GALs (generic array logic such as GAL22V10) overcome these limitations.

11.PALs and GALs with configurable architecture have outputs that can be combinational or registered, with various input or

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