Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

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12.Configurable output circuits in a PLD are called output logic macrocells (OLMCs) or just macrocells.

13.Macrocells are configured by programming architecture cells. Global architecture cells affect all macrocells in a device. A local architecture cell affects only the macrocell in which it is found.

14.GALs and Universal PALs have global control signals, such as clock, clear, and output enable, that can be applied to all macrocells in the device.

15.A GAL22V10 has ten macrocells, a global clock that can be used as a combinational input for nonclocked designs, and eleven dedicated inputs.

16.The GAL22V10 macrocells are not all the same size. There are two macrocells with each of the following numbers of product terms: 8, 10, 12, 14, 16.

17.PLDs that can be programmed while installed in a circuit are called in-system programmable (ISP). They are programmed by a 4-wire interface that complies to a standard published by the Joint Test Action Group (JTAG) and the IEEE (Std. 1149.1).

18.An Altera MAX7000S CPLD consists of groups of 16 macrocells, called Logic Array Blocks (LABs), that are interconnected by an internal bus called a Programmable Interconnect Array (PIA).

19.The number of macrocell outputs in an LAB that are connected to I/O pins depends on the CPLD package type. Macrocells that do not have external connections can still be used for buried logic function.

20.MAX7000S devices have four programmable control pins: global clock (GCLK1), Global Output Enable (OE1), Global Clear (GCLRn), and a pin that can be configured as a second global clock (GCLK2) or as a second global output enable (OE2). If these functions are not used, the associated pins can be used as standard I/Os.

21.If the ISP capability of a CPLD is to be used, there are four fewer pins available on the CPLD for user I/O.

G L O S S A R Y

21.If the ISP capability of a CPLD is to be used, there are four fewer pins available on the CPLD for user I/O.

22.Each MAX7000S macrocell has five dedicated product lines and capability to borrow or share additional product terms with neighboring macrocells in the same LAB.

23.Shared logic expanders allow one product term per macrocell to be shared with other macrocells in the LAB, totaling 16 product terms per LAB. The expander inverts the product term and feeds it back into the LAB AND matrix.

24.Parallel logic expanders allow a macrocell to borrow product lines from neighboring macrocells. These borrowed product lines are only available to one macrocell.

25.Expander assignments are done automatically by MAX PLUS II at compile time.

26.MAX7000S devices are based on EEPROM cells and are thus nonvolatile.

27.The Altera FLEX10K series of CPLDs is based on a look-up table (LUT) architecture. A look-up table consists of a 16-bit array of storage elements that are selected by four logic inputs.

28.An LUT combined with switching, configuration, and expansion circuitry comprises a logic element (LE), whose function is equivalent to a macrocell in an SOP-type device.

29.Eight logic elements and a local interconnect make up a Logic Array Block (LAB).

30.LABs in a FLEX10K device are interconnected by global row and column busses.

31.The number of inputs in a logic function can be expanded beyond the capacity of one logic element by using cascade chains.

32.Carry chains can be used to more efficiently implement carry functions in adders, counters, and comparators.

33.FLEX10K devices are based on SRAM technology and are therefore volatile; they must be reconfigured each time power is applied to the circuit.

Architecture cell A programmable cell that, in combination with other architecture cells, sets the configuration of a macrocell.

Buried logic Logic circuitry in a PLD that has no connection to the input or output pins of the PLD, but is used solely as internal logic.

Carry chain A circuit in a CPLD that is optimized for efficient operation of carry functions between logic elements.

Cascade chain A circuit in a CPLD that allows the input width of a Boolean function to expand beyond the width of one logic element.

Cell A fuse location in a programmable logic device, specified by the intersection of an input line and a product line.

Checksum An error-checking code derived from the accumulating sum of the data being checked.

CPLD Complex programmable logic device. A programmable logic device consisting of several interconnected programmable blocks.

Embedded array block (EAB) A relatively large block of storage elements in a CPLD (2048 bits in a FLEX10K device), used for implementing complex logic functions in look-up table format.

Generic array logic (GAL) A type of programmable logic device whose outputs can be configured as combinational or registered and whose programming matrix is based on electrically erasable logic cells.

Global architecture cell An architecture cell that affects the configuration of all macrocells in a device.

Global clock A clock signal in a PLD that clocks all registered outputs in the device.

I/O Control Block A circuit in an Altera CPLD that controls the type of tristate switching used in a macrocell output.

Input line A line which applies the true or complement form of an input variable to the AND matrix of a PLD.

Input line number A number assigned to a true or complement input line in a PAL AND matrix.

In-system programmability (ISP) The ability of a PLD to be programmed through a standard four-wire interface while installed in a circuit.

JEDEC Joint Electron Device Engineering Council

JEDEC file An industry standard form of text file indicating which fuses are blown and which are intact in a programmable logic device.

JTAG Port A four-wire interface specified by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit.

Local architecture cell An architecture cell that affects the configuration of one macrocell only.

Logic Array Block (LAB) A group of macrocells that share common resources in a CPLD.

Logic element (LE) A circuit internal to a CPLD used to implement a logic function as a look-up table.

Look-up table (LUT) A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations.

Multiplexer A circuit which selects one of several signals to be directed to a single output.

can be programmed for a variety of input or output configurations, such as active HIGH or active LOW, combinational, or registered. Often just called a macrocell.

PAL Programmable array logic. Programmable logic with a fixed OR matrix and a programmable AND matrix.

Problems 361

Parallel logic expanders Product terms that are borrowed from neighboring macrocells in the same LAB.

Product line A single line on a logic diagram used to represent all inputs to an AND gate (i.e., one product term) in a PLD sum-of-products array.

Product line first cell number The lowest cell number on a particular product line in a PAL AND matrix where all cells are consecutively numbered.

Programmable Interconnect Array (PIA) An internal bus with programmable connections that link together the Logic Array Blocks of a CPLD.

Programmable logic device (PLD) A logic device whose function can be programmed by the user, usually in sum-of- products form.

Register A digital circuit such as a flip-flop that stores one or more bits of digital information.

Registered output An output of a programmable array logic (PAL) device having a flip-flop (usually D-type) which stores the output state.

Shared logic expanders Product terms that are inverted and fed back into the programmable AND matrix of an LAB for use by any other macrocell in the LAB.

Text file An ASCII-coded document stored on a magnetic disk.

Universal PAL A PLD based on erasable cells and configurable outputs, much like GAL, but primarily designed to emulate PAL devices, such as PAL16L8.

Problem numbers set in color indicate more difficult problems; those with underlines indicate most difficult problems.

Section 8.1 Introduction to Progammable Logic

Section 8.2 PAL Fuse Matrix and Combinational

Outputs

Section 8.3 PAL Outputs With Programmable Polarity

8.1Draw a diagram showing the basic configuration and symbology for a PLD sum-of-products array.

8.2Draw a basic PAL circuit having four inputs, eight product terms, and one active-LOW combinational output. Draw fuses on your diagram showing how to make the following Boolean expression:

F A B C B C D A C D A C D

8.3Modify the PAL circuit drawn in Problem 8.2 to make two outputs having eight product terms and programmable polarity. Draw fuses on the diagram for each of the following functions:

F1 A B C B C D A C D A C DF2 A B C B C D A C D A C D

8.4Make a photocopy of Figure 8.8 (PAL20P8 logic diagram). Draw fuses on the PAL20P8 logic diagram showing how to make a BCD-to-2421 code converter, as developed in Example 3.22.

Table 8.3 shows how the two codes relate to each other. The equations are listed on page 362.

Table 8.3 BCD and 2421 Code

The Boolean equations for the BCD-to-2421 decoder are:

Y4 D4 D3D2 D3D1

Y3 D4 D3D2 D3D1

Y2 D4 D3D2 D3D2D1

Y1 D1

8.5 Repeat Problem 8.4 for a 2421-to-BCD code converter.

8.4PAL Devices with Registered Outputs

8.6What is a registered output?

8.7State the number of registered outputs for each of the following PAL devices:

a.PAL16R4

b.PAL16R6

c.PAL16R8

8.5Universal PAL and Generic Array Logic (GAL)

8.8Name two features of a PALCE16V8 that make it superior to a PAL16L8.

8.9State the difference between a global architecture cell and a local architecture cell in a PALCE16V8.

8.10How many macrocells are there in a GAL22V10? How many product lines do these macrocells have?

8.11State the four configurations possible with a macrocell in a GAL22V10.

8.12Is there a global output enable function available for a PALCE16V8? For a GAL22V10?

8.13Can the registered outputs of a PALCE16V8 be clocked by a product term function from the PAL AND matrix?

8.14Can the registered outputs of a GAL22V10 be clocked by a product term function from the GAL AND matrix?

8.15Are the Asynchronous Reset (AR) and Synchronous Preset (SP) functions in a GAL22V10 global or local? Explain your answer in one sentence.

8.6MAX7000S CPLD

8.16State one way in which a Complex PLD, such as an Altera MAX7000S, differs from a low-density PAL or GAL.

8.17How many macrocells are available in the following CPLDs:

a.EPM7032

b.EPM7064

c.EPM7128S

d.EPM7160S

8.18Which of the CPLDs listed in Problem 8.17 are in-system programmable? What does it mean when a device is insystem programmable?

8.19How many logic array blocks (LABs) are there in an Altera MAX7000S CPLD?

8.20How many user I/O pins are there in an EPM7128SLC84 CPLD? How many pins per LAB does this represent?

8.21What can be done with the macrocells in an LAB that do not connect to I/O pins?

8.22State the possible clock configurations of a MAX7000S macrocell.

8.23State the possible reset configurations of a MAX7000S macrocell.

8.24State the possible preset configurations of a MAX7000S macrocell.

8.25How many dedicated product terms are available in a MAX7000S macrocell? How can this number of product terms be supplemented? What is the maximum number of product terms available to a macrocell?

8.26How many shared logic expanders are available in an LAB?

8.7FLEX10K CPLD

8.27Briefly state the difference between CPLDs having sum- of-products architecture and look-up table architecture.

8.28How many inputs can a look-up table accept in an Altera FLEX10K logic element? How can this be expanded?

8.29What is the purpose of the carry chain in a FLEX10K CPLD?

8.30How many logic elements are there in a FLEX10K LAB?

8.31How many bits of storage are there in an Embedded Array Block in a FLEX10K CPLD?

O U T L I N E

9.1Basic Concepts of Digital Counters

9.2Synchronous Counters

9.3Design of Synchronous Counters

9.4Programming Binary Counters in VHDL

9.5Control Options for Synchronous Counters

9.6Programming Presettable and Bidirectional Counters in VHDL

9.7Shift Registers

9.8Programming Shift Registers in VHDL

9.9Shift Register Counters

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter you will be able to:

•Determine the modulus of a counter.

•Determine the number of outputs required by a counter for a given modulus.

•Determine the maximum modulus of a counter, given the number of circuit outputs.

•Draw the count sequence table, state diagram, and timing diagram of a counter.

•Determine the recycle point of a counter’s sequence.

•Calculate the frequencies of each counter output, given the input clock frequency.

•Draw a circuit for any full sequence synchronous counter.

•Determine the count sequence, state diagram, timing diagram, and modulus of any synchronous counter.

•Complete the state diagram of a synchronous counter to account for unused states.

•Design the circuit of a truncated sequence synchronous counter, using flipflops and logic gates.

•Use MAX PLUS II to create a graphic design file for any synchronous counter circuit.

•Use behavioral descriptions in VHDL to design synchronous counters of any modulus.

•Use a parameterized counter from the Library of Parameterized Modules in a VHDL file.

•Use the MAX PLUS II simulation tool to verify the operation of synchronous counters.

•Implement various counter control functions, such as parallel load, clear, count enable, and count direction, both in Graphic Design Files and in VHDL.

•Design a circuit to decode the output of the counter, both in a MAX PLUS II Graphic Design File or in VHDL.

•Draw a logic circuit of a serial shift register and determine its contents over time given any input data.