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C H A P T E R 9 • Counters and Shift Registers |
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Count_Logic |
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AND2 |
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NOT |
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DFF |
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LOAD |
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INPUT |
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OR2 |
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PRN OUTPUT
INPUT
P3
INPUT CLRN
CLOCK
FIGURE 9.23
Count/Load Selection
count logic (the next-state combinational circuit) or load an external value. The flip-flop shown is the most significant bit of a 4-bit binary counter, such as shown in Figure 9.19, but with the count logic represented only by an input pin. (For the fourth bit of a counter, the Boolean equation of the count logic is given by D3 Q3 Q2Q1Q0. It is left out in order to more clearly show the operation of the count/load function select circuit.)
The LOAD input selects whether the flip-flop synchronous input will be fed by the count logic or by the parallel input P3. When LOAD 0, the upper AND gate steers the count logic to the flip-flop, and the count progresses with each clock pulse. When LOAD 1, the lower AND gate loads the logic level at P3 directly into the flip-flop on the next clock pulse.
Count logic |
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AND3 |
XOR |
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INPUT |
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Q2 |
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INPUT |
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Q1 |
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INPUT |
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Q0 |
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AND2 |
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INPUT |
NOT |
DFF |
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LOAD |
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OR2 |
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PRN |
OUTPUT |
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AND2 |
D |
Q |
Q3 |
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P3 |
INPUT |
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CLRN |
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CLOCK |
INPUT |
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RESET |
INPUT |
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FIGURE 9.24
Counter Element with Synchronous Load and Asynchronous Clear
sl_count.gdf 4bit_sl.gdf 4bit_sl.scf
logic. If we leave out the used as a general element 9.26 shows the logic dia-
gram of a 4-bit synchronously presettable counter consisting of four instances of the counter element of Figure 9.25 and appropriate AND gates for a synchronous counter. This diagram implements a synchronous counter like that of Figure 9.19, but also incorporates a synchronous load function.
Figure 9.27 shows a simulation of the counter in Figure 9.26. The first 19 clock pulses drive the counter through its normal 4-bit cycle from 0H to FH, then up to 2H. At this point, we set the LOAD input HIGH and the value at the P inputs (9H) is loaded into the counter on the rising edge of the next clock pulse. An asynchronous RESET pulse at 880 ns drives the counter outputs to 0H, after which the count resumes.
9.5 • Control Options for Synchronous Counters |
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XOR |
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COUNT |
INPUT |
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AND2 |
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INPUT |
NOT |
DFF |
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LOAD |
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OR2 |
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PRN |
OUTPUT |
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AND2 |
D |
Q |
Q |
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P |
INPUT |
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CLRN |
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CLOCK |
INPUT |
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RESET |
INPUT |
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FIGURE 9.25
Counter Element with Synchronous Load and Asychronous Reset (sl_count)
AND3 |
sl_count |
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COUNT |
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LOAD |
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OUTPUT |
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P3 |
P |
Q |
Q3 |
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CLOCK |
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RESET |
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AND2 |
sl_count |
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COUNT |
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LOAD |
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OUTPUT |
INPUT |
P |
Q |
P2 |
Q2 |
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CLOCK |
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RESET |
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sl_count |
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COUNT |
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INPUT |
LOAD |
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OUTPUT |
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P1 |
P |
Q |
Q1 |
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CLOCK |
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RESET |
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VCC |
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sl_count |
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COUNT |
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INPUT |
LOAD |
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LOAD |
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OUTPUT |
INPUT |
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Q |
P0 |
P |
Q0 |
INPUT |
CLOCK |
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CLOCK |
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INPUT |
RESET |
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RESET |
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FIGURE 9.26
4-bit Counter with Synchronous Load and Asynchronous Reset
392 C H A P T E R 9 • Counters and Shift Registers
FIGURE 9.27
Simulation of 4-bit Counter with Synchronous Load and Asynchronous Reset
Asynchronous Load
The asynchronous load function of a counter makes use of the asynchronous preset and clear inputs of the counter’s flip-flops. Figure 9.28 shows the circuit implementation of the asynchronous load function, without any count logic.
When ALOAD (Asynchronous LOAD) is HIGH, both NAND gates in Figure 9.28 are enabled. If the P input is HIGH, the output of the upper NAND gate goes LOW, activating the flip-flop’s asynchronous PRESET input, thus setting Q 1. The lower NAND gate has a HIGH output, thus deactivating the flip-flop’s CLEAR input.
If P is LOW the situation is reversed. The upper NAND output is HIGH and the lower NAND has a LOW output, activating the flip-flop’s CLEAR input, resetting Q. Thus, Q will be the same value as P when the ALOAD input is asserted. When ALOAD is not asserted ( 0), both NAND outputs are HIGH and thus do not activate either the preset or clear function of the flip-flop.
Figure 9.29 shows the asynchronous load circuit with an asynchronous clear (reset) function added. The flip-flop can be cleared by a logic LOW either from the P input (via the lower NAND gate) or the CLEAR input pin. The clear function disables the upper NAND gate when it is LOW, preventing the flip-flop from being cleared and preset simultaneously. This extra connection also ensures that the clear function has priority over the load function.
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NAND2 |
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P |
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INPUT |
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ALOAD |
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DFF |
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COUNT |
INPUT |
D |
PRN |
OUTPUT |
INPUT |
Q |
Q |
CLK |
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NAND2 |
CLRN |
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NOT |
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FIGURE 9.28
Asynchronous LOAD Element
9.5 • Control Options for Synchronous Counters |
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INPUT |
NAND3 |
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P |
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ALOAD |
INPUT |
DFF |
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D |
INPUT |
D |
PRN |
OUTPUT |
INPUT |
Q |
Q |
CLK |
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NAND2 |
BNOR2 |
CLRN |
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NOT |
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CLEAR |
INPUT |
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FIGURE 9.29
Asynchronous LOAD Element with Asynchronous Clear
EXAMPLE 9.6 |
Use MAX PLUS II to redraw the circuit in Figure 9.29 to create a general element called |
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al_count that can be used in a synchronous counter with asynchronous load and clear. (Re- |
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similar element with synchronous load.) |
al_count.gdf
shows the modified circuit, which includes an XOR gate for part of the count logic. The remainder of the count logic must be supplied externally to this element for each bit of the counter.
INPUT |
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NAND3 |
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INPUT |
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XOR |
DFF |
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INPUT |
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D |
PRN |
OUTPUT |
INPUT |
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Q |
Q |
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NAND2 |
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CLRN |
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NOT |
BNOR2 |
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INPUT |
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9.30
9.6
Element with Asynchronous Load and Clear (al_count)
9.7
4bit_al.gdf 4bit_al.scf
Draw a circuit with four instances of al_count (from Example 9.6) to make a 4-bit synchronous counter with asynchronous load and reset. Create a simulation that tests the function of the counter.
Solution Figure 9.31 shows the circuit. (Compare this circuit to the counter with synchronous load in Figure 9.26. This difference between the two is in the load function, not the count logic.)
The Boolean function applied to the COUNT input of each instance of al_count consists of the logical product of all previous output bits. (COUNT3 Q2Q1Q0, COUNT2 Q1Q0, COUNT1 Q0, COUNT0 1.) When combined with the XOR at the COUNT input
