Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

400 C H A P T E R 9 • Counters and Shift Registers

WHEN 6,

WHEN 7,

CD: decode16.vhd WHEN 8,

4bit_dcd.gdf

x“FFBF” WHEN 9,

4bit_dcd.scf

x“FFDF” WHEN 10, x“FFEF” WHEN 11, x“FFF7” WHEN 12, x“FFFB” WHEN 13, x“FFFD” WHEN 14, x“FFFE” WHEN 15, X“FFFF” WHEN others;

END a;

The decoder has 16 outputs, one for each state of the counter. For each state, one and only one output will be low. (Refer to the section on binary decoders in Chapter 5 for a more detailed description of n-line-to-m-line binary decoders.)

Figure 9.41 shows a portion of the simulation waveforms (i.e., only the count value and the decoder outputs) for the circuit in Figure 9.40. As the count progresses up or down, as shown by the waveform for Q[3..0], the decoder outputs respond by going LOW in sequence.

Output decoders for binary counters can also be configured to have active HIGH outputs. In this case, one and only one output would be HIGH for each output state of the counter.

Terminal Count and RCO

A special case of output decoding is a circuit that will detect the terminal count, or last state, of a count sequence and activate an output to indicate this state. The terminal count depends on the count sequence. A 4-bit binary UP counter has a terminal count of 1111; a 4-bit binary DOWN counter has a terminal count of 0000. A circuit to detect these conditions must detect the maximum value of an UP count and the minimum value of a DOWN count.

FIGURE 9.41

Simulation of 4-bit Decoder

402 C H A P T E R 9 • Counters and Shift Registers

FIGURE 9.44

Counter Expansion Using RCO

The NAND gate in Figure 9.43 is enabled upon terminal count and passes the clock signal through to RCO. The NAND output sits HIGH when inhibited. The clock is inverted in the RCO circuit so that when the NAND gate inverts it again, the circuit generates a clock pulse in true form.

Figure 9.45 shows the simulation of the circuit of Figure 9.43. In the first half of the simulation, the counter is counting DOWN. The terminal count decoder output, MAX_MIN, goes HIGH when Q3Q2Q1Q0 0000. RCO generates a pulse at that time. For the second half, the counter is counting UP. MAX_MIN is HIGH when Q3Q2Q1Q0 1111 and RCO generates a pulse at that time.

FIGURE 9.45

Simulation of a 4-bit Bidirectional Counter with Terminal Count Detection

Note that the RCO pulse appears to be half the width of the MAX_MIN pulse. Although the NAND gate that generates RCO is enabled for the whole MAX_MIN pulse, the clock input is HIGH for the first half-period, which is the same as the RCO inhibit level.

The positive edge of RCO is at the end of the pulse. The idea is to synchronize the positive edge of the clock with the positive edge of RCO. However, since the RCO decoder is combinational, a propagation delay of about 7 ns is introduced.

SECTION 9.5 REVIEW PROBLEM

9.5Figure 9.46 shows two presettable counters, one with asynchronous load and clear, the other with synchronous load and clear. The counter with asynchronous functions has a 4-bit output labeled QA. The synchronously loaded counter has a 4-bit output labeled QS. The load and reset inputs to both counters are active LOW.

FIGURE 9.46

Section Review Problem 9.5

Two Presettable Counters

FIGURE 9.47

Timing Diagram for Counters in Figure 9.46

Figure 9.47 shows a partial timing diagram for the counters. Complete the diagram.

9.6Programming Presettable and Bidirectional Counters in VHDL

The presettable counters and bidirectional counters described in the previous section can be easily implemented in VHDL, either as behavioral descriptions or as LPM components. We will initially examine the behavioral descriptions of two counters, one with asynchronous load and clear and one with synchronous load and clear. We will then examine some options available in the module lpm_counter.