Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

SOLUTION

a.Boolean expression: Y A B

Shape: OR (at least one)

Input: HIGH Output: LOW

Descriptive sentence: Output Y is LOW if A OR B is HIGH.

b.Boolean expression: Y A B

Shape: AND (all)

Input: LOW Output: HIGH

Descriptive sentence: Output Y is HIGH if A AND B are LOW.

Both gates in this example yield the same truth table. Therefore they are DeMorgan

The gates in Figures 2.22 and 2.24 yield the following algebraic equivalencies:

A B A BA B A B

These equivalencies are known as DeMorgan’s theorems. (You can remember how to use DeMorgan’s theorems by a simple rhyme: “Break the line and change the sign.”)

It is tempting to compare the first gate in Figure 2.22 and the second in Figure 2.24 and declare them equivalent. Both gates are AND-shaped, both have inversions. However, the comparison is false. The gates have different truth tables, as we have found in Tables 2.11 and 2.13. Therefore they have different logic functions and are not equivalent. The same is true of the OR-shaped gates in Figures 2.22 and 2.24. The gates may look similar, but since they have different truth tables, they have different logic functions and are therefore not equivalent.

The confusion arises when, after changing the logic input and output levels, you forget to change the shape of the gate. This is a common, but serious, error. These inequalities can be expressed as follows:

A B A BA B A B

SOLUTION

Boolean expression: Y A B C

Shape: OR (at least one)

Input: LOW

Output: LOW

Descriptive sentence: Output Y is LOW if A OR B OR C is LOW.

Figure 2.26 shows the DeMorgan equivalent form of the gate in Figure 2.25. To create this symbol, we change the shape from OR to AND and invert the logic levels at both input and output.

Boolean expression: Y ABC

Descriptive sentence: Output Y is HIGH if A AND B AND C are HIGH.

SECTION 2.4 REVIEW PROBLEM

2.8 The output of a gate is described by the following Boolean expression:

Y A B C D

Write the Boolean expression for the DeMorgan equivalent form of this gate.

2.5 Enable and Inhibit Properties of Logic Gates

K E Y T E R M S

Digital signal (or pulse waveform) A series of 0s and 1s plotted over time.

True form Not inverted.

Complement form Inverted.

Enable A logic gate is enabled if it allows a digital signal to pass from an input to the output in either true or complement form.

Inhibit (or disable) A logic gate is inhibited if it prevents a digital signal from passing from an input to the output.

In phase Two digital waveforms are in phase if they are always at the same logic level at the same time.

Out of phase Two digital waveforms are out of phase if they are always at opposite logic levels at any given time.

In Chapter 1, we saw that a digital signal is just a string of bits (0s and 1s) generated over time. A major task of digital circuitry is the direction and control of such signals. Logic gates can be used to enable (pass) or inhibit (block) these signals. (The word “gate” gives a clue to this function; the gate can “open” to allow a signal through or “close” to block its passage.)

AND and OR Gates

The simplest case of the enable and inhibit properties is that of an AND gate used to pass or block a logic signal. Figure 2.27 shows the output of an AND gate under different conditions of input A when a digital signal (an alternating string of 0s and 1s) is applied to input B.

FIGURE 2.27

Enable/Inhibit Properties of an

AND Gate

Recall the properties of an AND gate: both inputs must be HIGH to make the output HIGH. Thus, if input A is LOW, the output must always be LOW, regardless of the state of input B. The digital signal applied to B has no effect on the output, and we say that the gate is inhibited or disabled. This is shown in the first half of the timing diagram in Figure 2.27.

If A AND B are HIGH, the output is HIGH. When A is HIGH and B is LOW, the output is LOW. Thus, output Y is the same as input B if input A is HIGH; that is, Y and B are in phase with each other. The input waveform is passed to the output in true form, and we say the gate is enabled. The last half of the timing diagram in Figure 2.27 shows this waveform.

It is convenient to define terms for the A and B inputs. Since we apply a digital signal to B, we will call it the Signal input. Since input A controls whether or not the signal

FIGURE 2.29

Example 2.4 OR Gate Enable/Inhibit Waveform

Example 2.4 shows that a gate can be in the inhibit state even if its output is HIGH. It is natural to think of the HIGH state as “ON,” but this is not always the case. Enable or inhibit states are determined by the effect the Signal input has on the gate’s output. If an input signal does not affect the gate output, the gate is inhibited. If the Signal input does affect the output, the gate is enabled.

NAND and NOR Gates

When inverting gates, such as NAND and NOR, are enabled, they will invert an input signal before passing it to the gate output. In other words, they transmit the signal in complement form. Figures 2.30 and 2.31 show the output waveforms of a NAND and a NOR gate when a square waveform is applied to input B and input A acts as a Control input.

FIGURE 2.30

Enable/Inhibit Properties of a

NAND Gate

FIGURE 2.31

Enable/Inhibit Properties of a

NOR Gate