Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

46C H A P T E R 2 • Logic Functions and Gates

2.6Integrated Circuit Logic Gates

K E Y T E R M S

Integrated circuit (IC) An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package.

Small scale integration (SSI) An integrated circuit having 12 or fewer gates in one package.

Medium scale integration (MSI) An integrated circuit having the equivalent of 12 to 100 gates in one package.

Large scale integration (LSI) An integrated circuit having from 100 to 10,000 equivalent gates.

Very large scale integration (VLSI) An integrated circuit having more than 10,000 equivalent gates.

Transistor-transistor logic (TTL) A family of digital logic devices whose basic element is the bipolar junction transistor.

Complementary metal-oxide-semiconductor (CMOS) A family of digital logic devices whose basic element is the metal-oxide-semiconductor field effect transistor (MOSFET).

Chip An integrated circuit. Specifically, a chip of silicon on which an integrated circuit is constructed.

Dual in-line package (DIP) A type of IC with two parallel rows of pins for the various circuit inputs and outputs.

Printed circuit board (PCB) A circuit board in which connections between components are made with lines of copper on the surfaces of the circuit board.

Breadboard A circuit board for wiring temporary circuits, usually used for prototypes or laboratory work.

Wire-wrap A circuit construction technique in which the connecting wires are wrapped around the posts of a special chip socket, usually used for prototyping or laboratory work.

Through-hole A means of mounting DIP ICs on a circuit board by inserting the

IC leads through holes in the board and soldering them in place.

Surface-mount technology (SMT) A system of mounting and soldering integrated circuits on the surface of a circuit board, as opposed to inserting their leads through holes on the board.

Small outline IC (SOIC) An IC package similar to a DIP, but smaller, which is designed for automatic placement and soldering on the surface of a circuit board. Also called gull-wing, for the shape of the package leads.

Thin shrink small outline package (TSSOP) A thinner version of an SOIC package.

Plastic leaded chip carrier (PLCC) A square IC package with leads on all four sides designed for surface mounting on a circuit board. Also called J-lead, for the profile shape of the package leads.

Quad flat pack (QFP) A square surface-mount IC package with gull-wing leads.

Ball grid array (BGA) A square surface-mount IC package with rows and columns of spherical leads underneath the package.

Data sheet A printed specification giving details of the pin configuration, electrical properties, and mechanical profile of an electronic device.

Data book A bound collection of data sheets. A digital logic data book usually contains data sheets for a specific logic family or families.

Portable document format (PDF) A format for storing published documents in compressed form.

All the logic gates we have looked at so far are available in integrated circuit form. Most of these small scale integration (SSI) functions are available either in transistortransistor logic (TTL) or complementary metal-oxide-semiconductor (CMOS) technologies. TTL and CMOS devices differ not in their logic functions, but in their construction and electrical characteristics.

TTL and CMOS chips are designated by an industry-standard numbering system. TTL devices and the more recent members of the CMOS family are numbered according to the general format 74XXNN, where XX is a family identifier and NN identifies the specific logic function. For example, the number 74ALS00 represents a quadruple 2-input NAND device (indicated by 00) in the advanced low power Schottky (ALS) family of TTL. (Earlier versions of CMOS had a different set of unrelated numbers of the form 4NNNB or 4NNNUB where NNN was the logic function designator. The suffixes B and UB stand for buffered and unbuffered, respectively.)

Table 2.21 lists the quadruple 2-input NAND function as implemented in different logic families. These devices all have the same logic function, but different electrical characteristics.

Table 2.21 Part Numbers for a Quad 2-input NAND Gate in Different Logic Families

Table 2.22 lists several logic functions available in the high-speed CMOS family. These devices all have the same electrical characteristics, but different logic functions.

Table 2.22 Part Numbers for Different Functions within a Logic Family (High-Speed CMOS)

Until recently, the most common way to package logic gates has been in a plastic or ceramic dual in-line package, or DIP, which has two parallel rows of pins. The standard spacing between pins in one row is 0.1 (or 100 mil). For packages having fewer than 28 pins, the spacing between rows is 0.3 (or 300 mil). For larger packages, the rows are spaced by 0.6 (600 mil).

This type of package is designed to be inserted in a printed circuit board in one of two says: (a) the pins are inserted through holes in the circuit board and soldered in place; or (b) a socket is soldered to the circuit board and the IC is placed in the socket. The latter method is more expensive, but makes chip replacement much easier. A socket can occasionally cause its own problems by making a poor connection to the pins of the IC.

The DIP is also convenient for laboratory and prototype work, since it can also be inserted easily into a breadboard, a special type of temporary circuit board with internal connections between holes of a standard spacing. It is also convenient for wire-wrapping, a technique in which a special tool is used to wrap wires around posts on the underside of special sockets.

48 C H A P T E R 2 • Logic Functions and Gates

FIGURE 2.36

14-Pin DIP (Top View)

The outline of a 14-pin DIP is shown in Figure 2.36. There is a notch on one end to show the orientation of the pins. When the IC is oriented as shown and viewed from above, pin 1 is at the top left corner and the pins number counterclockwise from that point.

Besides DIP packages, there are numerous other types of packages for digital ICs, including, among others, small outline IC (SOIC), thin shrink small outline package (TSSOP), plastic leaded chip carrier (PLCC), quad flat pack (QFP), and ball grid array (BGA) packages. They are used mostly in applications where circuit board space is at a premium and in manufacturing processes relying on surface-mount technology (SMT). In fact, these devices represent the majority of IC packages found in new designs. Some of these IC packaging options are shown in Figure 2.37.

FIGURE 2.37

Some IC Packaging Options

SMT is a sophisticated technology which relies on automatic placement of chips and soldering of pins onto the surface of a circuit board, not through holes in the circuit board. This technique allows a manufacturer to mount components on both sides of a circuit board.

Primarily due to the great reduction in board space requirements, most new ICs are available only in the newer surface-mount packages and are not being offered at all in the DIP package. However, we will look at DIP offerings in logic gates because they are inexpensive and easy to use with laboratory breadboards and therefore useful as a learning tool.

Logic gates come in packages containing several gates. Common groupings available in DIP packages are six 1-input gates, four 2-input gates, three 3-input gates, or two 4-in- put gates, although other arrangements are available. The usual way of stating the number of logic gates in a package is to use the numerical prefixes hex (6), quad or quadruple (4), triple (3), or dual (2).

Some common gate packages are listed in Table 2.23.

Table 2.23 Some Common Logic Gate ICs

Information about pin configurations, electrical characteristics, and mechanical specifications of a part is available in a data sheet provided by the chip manufacturer. A collection of data sheets for a particular logic family is often bound together in a data book. More recently, device manufacturers have been making data sheets available on their corporate World Wide Web sites in portable document format (PDF), readable by a special program such as Adobe Acrobat Reader. Links to some of these manufacturers can be found on the Online Companion Web site for this book. (http://www.electronictech.com)

Figure 2.38 shows the internal diagrams of gates listed in Table 2.23. Notice that the gates can be oriented inside a chip in a number of ways. That is why it is important to confirm pin connections with a data sheet.

In addition to the gate inputs and outputs there are two more connections to be made on every chip: the power (VCC) and ground connections. In TTL, connect VCC to 5 Volts and GND to ground. In CMOS, connect the VCC pin to the supply voltage ( 3 V to 6 V) and GND to ground. The gates won’t work without these connections.

Every chip requires power and ground. This might seem obvious, but it’s surprising how often it is forgotten, especially by students who are new to digital electronics. Probably this is because most digital circuit diagrams don’t show the power connections, but assume that you know enough to make them.

The only place a chip gets its required power is through the VCC pin. Even if the power supply is connected to a logic input as a logic HIGH, you still need to connect it to the power supply pin.

Even more important is a good ground connection. A circuit with no power connection will not work at all. A circuit without a ground may appear to work, but it will often produce bizarre errors that are very difficult to detect and repair.

In later chapters, we will work primarily with complex ICs in PLCC packages. The power and ground connections are so important to these chips that they will not be left to chance; they are provided on a specially designed circuit board. Only input and output pins are accessible for connection by the user.

As digital designs become more complex, it is increasingly necessary to follow good practices in board layout and prototyping procedure to ensure even minimal functionality.