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Solution Refer to the 74HC00A data sheet in Appendix C.

a.PD VCC ICC (5 V)(1 A) 5 W. This is the quiescent power dissipation of the circuit.

b.The 74HC00A data sheet indicates that each gate has a maximum input capacitance, Cin of 10 pF. Assume that this value represents the load capacitance of gates 1, 2, and 3 of the circuit in Figure 11.12. Further assume that gate 4 has a load capacitance of 0. The total power dissipation of the circuit is given by:

PD 3(22 pF 10 pF)(5 V)2 (0.01 MHz)

(22 pF)(5 V)2 (0.01 MHz) 5 W

3(8 W) 5.5 W 5 W

34.5 W

c.For f 1 MHz, total power dissipation is given by:

PD 3(22 pF 10 pF)(5 V)2 (1 MHz)

(22 pF)(5 V)2 (1 MHz) 5 W

3(800 W) 550 W 5 W

2955 W 2.95 mW

CPD 22 pF per gate

CL 10 pF for 3 gates and 0 pF for 1 gate

Total: PD (3(10pF 22 pF) 22 pF)(5 V)2f

(3(32 pF) 22 pF) (25 V2) f

(96 pF 22 pF) (25 V2) f (118 pF) (25 V2) f

For PD 15 mW:

15mW

f 2 5.08MHz (118pF)(25V )

The power dissipation of the 74HC00 circuit exceeds that of the 74LS00 circuit at 5.08

MHz.

N O T E

The power saving in a high-speed CMOS circuit generally results from the fact that most device outputs are not switching at any given time. The power dissipation of a TTL circuit is independent of frequency and therefore draws some power at all times. This is not the case for CMOS, which draws the majority of its power when switching.

514 C H A P T E R 1 1 • Logic Gate Circuitry

SECTION 11.4 REVIEW PROBLEM

11.4 Why does CMOS power dissipation increase with frequency?

11.5Noise Margin

K E Y T E R M S

Noise Unwanted electrical signal, often resulting from electromagnetic radiation.

Noise margin A measure of the ability of a logic circuit to tolerate noise.

Electrical circuits are susceptible to noise, or unwanted electrical signals. Such signals are often induced by electromagnetic fields of motors, fluorescent lighting, highfrequency electronic circuits, and cosmic rays. They can cause erroneous operation of a digital circuit. Since it is impossible to eliminate all noise from a circuit, it is desirable to build a certain amount of tolerance, or noise margin, into digital devices used in the circuit.

In all circuits studied so far, we have assumed that logic HIGH is 5 volts and logic LOW is 0 volts in devices with a 5-volt supply. In practice, there is a certain amount of tolerance on both the logic HIGH and LOW voltages; for TTL devices, a HIGH at a device input is anything above about 2 volts, and a LOW is any voltage below about 0.8 volts. Due to internal voltage drops, the HIGH output of a TTL gate is typically about3.5 volts.

Figure 11.13 shows one inverter driving another. In Figure 11.13a, the output of the first inverter and the input of the second have the same logic threshold. That is, the input of the second gate recognizes any voltage above 2.7 volts as HIGH (VIH 2.7 V) and any voltage below 0.5 volts as LOW (VIL 0.5 V). The output of the first inverter produces at least 2.7 volts when HIGH (VOH 2.7 V) and no more than 0.5 volts as LOW

(VOL 0.5 V).

If there is noise on the line connecting the two gates, it will likely cause the voltage of the second gate input to penetrate into the forbidden region between logic HIGH and LOW levels. This is shown on the graph of the waveform in Figure 11.13a. When the voltage enters the forbidden region, the gate will not operate reliably. Its output may switch states when it is not supposed to.

Figure 11.13b shows the same circuit with different logic thresholds at input and output. The output of the first inverter is guaranteed to be at least 2.7 volts when HIGH (VOH 2.7 V) and no more than 0.5 volts when LOW (VOL 0.5 V). The second gate recognizes any input voltage greater than 2 volts as a HIGH (VIH 2 V) and any input voltage less than 0.8 volts (VIL 0.8 V) a LOW.

The difference between logic thresholds allows for a small noise voltage, equal to or less than the difference, to be superimposed on the desired signal. It will not cause the input voltage of the second inverter to penetrate the forbidden region. This ensures reliable operation even in the presence of some noise.

For the 74LS04 inverter, the HIGH-state and LOW-state noise margins, VNH and VNL, are:

VNH VOH VIH 2.7 V 2.0 V 0.7 V

VNL VIL VOL 0.8 V 0.5 V 0.3 V

A device with these values of VIH and VIL is deemed to be TTL compatible.

FIGURE 11.13

Noise Margins

EXAMPLE 11.12 Use the 74HC00A data sheet in Appendix C to calculate the noise margins for this gate. Assume VCC 4.5 V, ambient temperature (TA) is 25°C, and the driving gate is fully loaded (IOUT 4 mA).

516 C H A P T E R 1 1 • Logic Gate Circuitry

SECTION 11.5 REVIEW PROBLEM

11.5 Calculate the noise margins of a 74HCT00A NAND gate from the data sheet in Appendix C. VCC 4.5 V, TA 25°C, IOUT 4 mA

11.6 Interfacing TTL and CMOS Gates

K E Y T E R M

TTL Compatible Able to be driven directly by a TTL output. Usually implies

voltage compatibility with TTL.

Interfacing different logic families is just an extension of the fanout and noise margin problems; you have to know what the load gates of a circuit require and what the driving gates can supply. In practice, this means you must know the specified values of input and output voltages and currents for the gates in question. Table 11.4, which is derived from the manufacturers’data sheets included inAppendix C, gives an overview of input and output parameters for a variety of TTL and CMOS families. Ambient temperature is assumed to be 25°C.

Table 11.4 TTL and CMOS Input and Output Parameters

Table 11.4 is useful for comparison of logic families, but it is not a substitute for reading data sheets, as it gives parameters only under a restricted set of conditions. We can, however, make some observations based on the data in Table 11.4.

1.Input currents in a CMOS gate are very low, due to its high input impedance. As a result fanout is generally not a problem with CMOS loads. Interface problems to CMOS loads have to do with input voltage, not current.

2.CMOS devices, such as 74HCT, that have the same values of VIH and VIL as the TTL families in Table 11.4, are considered to be TTL compatible, since they can be driven directly by TTL drivers.

3.LSTTL is usually regarded as the benchmark for measuring TTL loading of a CMOS circuit. For example, a data sheet will claim that a device can drive 10 LSTTL loads.

This claim depends on the values of IOH and IOL for the driving gate, which are not listed directly in CMOS data sheets, except as absolute maximum ratings. The values in

Table 11.4 are the values of current for which the output voltages, VOH and VOL, are defined. (Recall from the section on fanout in this chapter that increasing output current causes output voltages to migrate away from their nominal values, thus reducing device noise margins.)

Let us examine four interfacing problems: high-speed CMOS driving 74LS, 74LS driving 74HC, 74LS driving 74HCT, and 74LS driving low-voltage CMOS.