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11.3 • Fanout

509

What happens if we load a gate output beyond its rated fanout? Adding more load

gates will do this by increasing the value of IOL beyond its maximum rating. If enough load

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is added, the output of the driving gate might be destroyed by the heat generated by the ex-

cess current. More likely, the performance of the driving gate will be degraded.

Figure 11.10 shows the relationship between output voltage and current for a 74LS00

and a 74F00 NAND gate. Figure 11.10a shows that the output voltage (LOW state) in-

creases with increasing sink current. Figure 11.10b indicates a decrease in HIGH state out-

put voltage with an increase of source current.

1

VOLTAGE (VOLTS)

0.5

, OUTPUT

OL

V

0

0

4

(VOLTS)

3

VOLTAGE

2

, OUTPUT

1

OH

V

0

FIGURE 11.10

TA = 25°C

VCC = 4.5 V

LS00

F00

20

40

60

IOL, OUTPUT CURRENT (mA)

a. Output low characteristic

TA = 25°C

VCC = 5.5 V

LS00

F00

–50

–100

–150

IOH, OUTPUT CURRENT (mA)

b. Output high characteristic

Output Characteristics of 74LS00 and 74F00 Gate. Reprinted with permission of Motorola

In other words, a greater load in either state takes the output voltage further away from its nominal value. This has an effect on other performance factors, such as noise margin, which we will examine in a later section of the chapter.

N O T E

The output voltage of a logic gate is defined in a datasheet for a particular value of output current.

We will examine the fanout of CMOS devices in a later section on interfacing between CMOS and TTL.

510 C H A P T E R 1 1 • Logic Gate Circuitry

SECTION 11.3 REVIEW PROBLEM

11.3The input and output currents IOH, IOL, IIH, and IIL of a TTL device may be classified as source currents or sink currents. List each input or output current as a source or sink current.

14.4Power Dissipation

K E Y T E R M S

Power dissipation The electrical energy used by a logic circuit in a specified period of time. Abbreviation: PD

VCC

TTL or high-speed CMOS supply voltage.

ICC

Total TTL or high-speed CMOS supply current.

ICCH

TTL supply current with all outputs HIGH.

ICCL

TTL supply current with all outputs LOW.

IT

When referring to CMOS supply current, the sum of static and dynamic supply

currents.

CPD

Internal capacitance of a high-speed CMOS device used to calculate its

power dissipation.

Electronic logic gates require a certain amount of electrical energy to operate. The measure of the energy used over time is called power dissipation. Each of the different families of logic has a characteristic range of values for the power it consumes.

For TTL and CMOS, the power dissipation is calculated as follows:

TTL:

PD VCC ICC

High-Speed CMOS:

PD VCC IT

(IT quiescent dynamic supply

current)

Figure 11.11 shows the supply voltage and current in a 74XX00 NAND gate.

FIGURE 11.11

Vcc

Power Supply Voltage and

Icc

Current in a 74XX00

NAND gate.

Icc

The main difference between the two families is the calculation of supply current. The supply current in a TTL device is different when its outputs are HIGH than when

they are LOW. Thus, supply current, ICC, and therefore power dissipation, depends on the states of the device outputs. If the outputs are switching, ICC is proportional to output duty cycle.

In a CMOS device, very little power is consumed when the device outputs are static. Much more current is drawn from the supply when the outputs switch from one state to another. Thus, the power dissipation of a device depends on the switching frequency of its outputs.

11.4 • Power Dissipation

511

Power Dissipation in TTL Devices

Two values are given for supply current in a TTL data sheet. ICCL is the current drawn from the power supply when all gate outputs are LOW. ICCH is the current drawn from the supply when all outputs are HIGH. If the gate outputs are not all at the same level, the supply current is the sum of currents given by:

nH

nL

ICC ICCH ICCL

n

n

where

n is the total number of gates in the package

nH is the number of gates whose output is HIGH

nL is the number of gates whose output is LOW

The power dissipation of a TTL chip also depends on the duty cycle of the gate out-

puts. That is, it depends on the fraction of time that the chip’s outputs are HIGH.

If we assume that, on average, the outputs of a chip are switching with a duty cycle of

50%, the supply current can be calculated as follows:

ICC (ICCH ICCL)/2

If the output duty cycle is other than 50%, the supply current is given by:

ICC DC ICCH (1 DC) ICCL

where DC duty cycle.

EXAMPLE 11.8

Figure 11.12 shows a circuit constructed from the gates in a 74XX00 quadruple 2-input

NAND gate package. Use the data sheet shown in Figure 11.3 to determine the maximum

power dissipation of the circuit if the input is DCBA 1001 and the gates are 74LS00

NANDs. Refer to the data sheets in Appendix C and repeat the calculation for 74ALS00

and 74AS00 gates.

FIGURE 11.12

Power Dissipation of 74XX00 NAND

Solution

Gate 1: AB 1

Gate 2: CD 1

Gate 3: AB CD 0

Gate 4: AB CD 1

Since three outputs are HIGH and one is LOW, the supply current is given by:

nH

nL

ICC ICCH ICCL

n

n

3 ICCH 1 ICCL

4

4

512 C H A P T E R 1 1 • Logic Gate Circuitry

Maximum supply current for each device is:

74LS00: ICC 0.75(1.6 mA) 0.25(4.4 mA) 2.3 mA 74ALS00: ICC 0.75(0.85 mA) 0.25(3 mA) 1.3875 mA 74AS00: ICC 0.75(3.2 mA) 0.25(17.4 mA) 6.75 mA

Maximum power dissipation for each device is:

74LS00: PD VCC ICC (5 V)(2.3 mA) 11.5 mW

74ALS00: PD VCC ICC (5V)(1.3875 mA) 6.94 mW

74AS00: PD VCC ICC (5V)(6.75 mA) 33.75 mW

(1 mW 1 milliwatt 10 3 W.)

EXAMPLE 11.9

Find the maximum power dissipation of the circuit in Figure 11.12 if the gates are 74LS00

and the gate outputs are switching with an average duty cycle of 30%.

Solution

ICC 0.3 ICCH 0.7 ICCL

ICC 0.3(1.6 mA) 0.7(4.4 mA)

3.56 mA

PD VCC ICC (5 V)(3.56 mA) 17.8 mW

Power Dissipation in High-Speed CMOS Devices

CMOS gates draw the most power when their outputs are switching from one logic state to

the other. When the outputs are static (not switching), the large internal impedances of the

gate limit the supply current. A change of state requires the charging and discharging of in-

ternal gate capacitances, resulting in a greater demand on the power supply current. Thus,

the faster a CMOS gate switches, the more current, and hence more power, it requires.

CMOS supply current has two components: a quiescent current that flows when the

gate is in a steady state and a dynamic component that depends on frequency. For relatively

high frequencies (about 1 MHz and up), the quiescent component is small compared to the

dynamic component and can be neglected.

The quiescent current is usually specified for an entire chip package, regardless of the

number of gates. It is given by ICC VCC. For a 74HC00A NAND gate, ICC 1 A at room

temperature for a supply voltage of VCC 6.0 V. The dynamic component calculation ac-

counts for internal and load capacitance and is given, per gate, by:

(CL CPD) VCC2 f

where

CL is the gate load capacitance

CPD is the gate internal capacitance

VCC is the supply voltage

f is the switching frequency of the gate output

EXAMPLE 11.10

The circuit in Figure 11.12 is constructed from 74HC00A high-speed CMOS NAND gates.

Calculate the power dissipation of the circuit:

a. When the gate inputs are steady at the state DCBA 1010

b. When the outputs are switching at an average frequency of 10 kHz c. When the outputs are switching at an average frequency of 1 MHz Supply voltage is 5 V. Temperature range is 25°C to 55°C.

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