Файл: Embedded Controller Hardware Design (Ken Arnold, 2000).pdf

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chip, and the load presented by the actual load capacitance. The capacitive load is the parallel combination of all the input capacitances of the gate inputs attached to the signal, plus the wiring capacitance. Since the capacitors in parallel are equivalent to a single capacitor equal to the sum of the individual capacitances, we just add up all the load capacitor values and compare this to the output’s specified test load. The driving device’s specified load capacitance, CL, the test load capacitance used by the manufacturer for specifying the AC or timing characteristics of the device. Most often, this specification is listed in the test conditions or notes for the timing specifications of the chip. As long as the sum of the load capacitances, including the stray wiring capacitance, is less than the specified test load for the driving device, all the timing specifications will be valid as specified in the timing section of the data sheet. If the driving device is overloaded (actual CL is greater than specified CL), then the timing specifications of the device need to be de-rated (slowed down), since additional capacitance will increase the rise and fall times of the signal line in question. Methods for estimating the amount that an overloaded output can withstand are described later.

AC characteristics of the outputs and the inputs consist of:

As long as the inequality below is satisfied, the signal will meet the timing specifications for the driving device. If the actual load is greater, it will delay:

Driving device spec CL > actual Cload = Cin1 + Cin2 + … + Cwiring

The AC fan-out is limited by the parallel combination of the logic inputs’ capacitance, Cin, and the stray or wiring capacitance. Capacitors in parallel are additive, so the load presented to an output is the sum of the input capacitances of the logic inputs plus the wiring capacitance. Logic input capacitance is often difficult to find, as it may not be listed in the component data sheet, but rather in another section of the data book describing the characteristics

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common to all members of a given logic family. Typical logic input capacitance ranges from 1 to 5 pF (picofarads or 10-12 F), but may be outside this range. The maximum load capacitance which a device is specified to drive (CL), is usually defined in the test conditions for the timing specifications of an integrated circuit, as it is the timing which is most affected by capacitance. Load capacitance is usually specified in the range of 50 to 150 pF. Wiring capacitance is often in the range of 1 to 2 pF per inch of wire for a nominal printed circuit trace. Actual values can vary quite a bit, depending upon

the physical dimensions of the trace, proximity to surrounding signals and distance from a ground plane, as well as the dielectric constant of the circuit board material.

Calculating Wiring Capacitance

The standard formula for determining capacitance is:

C = (ε * A)/d

Where A is the area of two closely spaced parallel plates, d is the distance between the plates, and e represents the permittivity of the material (permittivity is the measure of how easily a material can carry electric lines of force).

For the purposes of this section, we can define the area, A, as the trace length multiplied by the trace width. Wiring capacitance is determined as a capacitance per unit length for a given trace width and distance from the ground or power plane.

Let’s examine a typical situation. For an eight layer PC board with 8 mil traces, and innermost layer ground/power planes, what is the capacitance per inch of trace on each of the signal layers?

Here are the terms we’ll use in the equations to solve this problem and their values:

•trace width (w) = 8 mils (one mil equals 10-3 inch)

•trace length (l) = 1000 mils

•area (A) = w times l

•total board thickness (T) = 0.062 inch

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•number of layers (N) = 8

•number of layers separating power and ground plane (n) = 1

•fringe effect and inter-trace stray capacitance adjustment factor (f) = 1.7

•permittivity of air (e) = 8.859*10-12*( coul2 / (newton*m2) )

•relative permittivity of glass-epoxy dielectric (er) used in this example = 6

We start by determining the thickness of each dielectric layer, represented by t:

t = T/(N - 1) = 8.857 mils

Next we need to determine the distance between the trace and ground/power plane, represented by d. This is found by the formula d = nt, which in this case makes for a simple calculation!

The capacitance as a function of the number of layers distance (Cd) is found by the formula:

Cd = (ε * ε r * A * f) / d

Using this formula,

C(1 * d) = 2.073 pF (layer closest to ground/power plane)

C(2 * d) = 1.037 pF (layer next closest to ground/power plane)

C(3 * d) = 0.691 pF (layer farthest from ground/power plane)

To find the average capacitance per inch (Cavg), then

Cavg = ( C(1 * d) + C(2 * d) + C(3 * d) )/ 3 = 1.267 pF

From this example, it is apparent that the stray wiring capacitance can vary significantly depending upon which layer of a multi-layer PC board a particular trace is located. Since a signal may travel on different layers between source and destination, exact values may be difficult to determine.

When performing a worst-case analysis of a given design, it is most effective to calculate the total load capacitance based on the sum of the loads’ input capacitances, plus an estimate of the nominal wiring capacitance using 1 or 2 picofarads per inch of wiring using a rough guess for the length of the trace.

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In a typical design, we might pick the diagonal distance from one corner of the board to the other, and multiply by 1 or 2 picofarads. If the total load capacitance is less than the driving device’s specified test load capacitance, then the device will perform as specified. If not, or if it’s very close, we might want to make a more accurate estimate, or avoid the problem by using a driving device that has a larger specified test load capacitance. Other alternatives include using two outputs from the same chip in parallel to double the drive capacity, or splitting the loads into two separate groups and driving them independently from two different sources.

As digital IC technology has improved, allowing signals to be processed at ever-increasing rates, the other non-ideal effects of the devices that could be ignored at lower speeds become more important. At very high speeds, these secondary effects become much more important. A wire ceases to be equivalent to a zero ohm connection with zero time delay. For the newer high-speed logic devices, the speed of the signal traveling down the wire, distributed resistance and inductance, as well as capacitance, may become very important. When the time it takes a signal to propagate down a wire are of the same order as the rise and fall time of the signal, it behaves as a transmission line, rather than an ideal wire. Transmission line effects are briefly described later in this chapter.

Fan-Out When CMOS Drives LSTTL

A common design problem involves the determination of how many LSTTL loads a CMOS output can drive. In this section, we will use the parameters below in an example to determine the number of LSTTL loads a CMOS gate can drive.

LSTTL gate DC Parameters:

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Absolute Maximum Operating Conditions:

Note: Test conditions RL = 5K, CL = 150 pF

For Logic One:

CMOS IOH = 600 microamperes ( A)

LSTTL IIH = 50 A so 600 A/50 A = 12 loads

For Logic zero:

CMOS IOL = 3.6 milliamperes (mA)

LSTTL IIL = 360 A so 3.6mA/360 A = 10 loads

Thus, considering the DC specifications only, the maximum number of loads driven is 10, since the zero state is the worst-case condition. The AC parameters would not be the limiting factor in this case, since the CMOS output is specified with a CL of 150 pF, and each LS input is only 10 pF. Thus, 10 loads would present 100 pF plus stray wiring capacitance of less than 50 pF would present an AC load less than the 150 pF CMOS output load handling capability.

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How many additional CMOS loads could be added? There are two levels of answer for this problem. First, from a DC point of view all the CMOS Iol output sink current is used up, so from this point of view, no loads could be added. However, there is negligible current in a CMOS input, so it is not the practical limit. In fact, the errors in the DC computations above are in excess of the amount required to drive a CMOS input, so in reality the DC current is not a problem. The real limitation is the capacitive loading. Even if you assume the loading from the TTL inputs and wiring can be ignored, the CMOS input capacitance will limit the loading. For the output to conform to the specs, the test load was specified as 150 pF (CL). With ten LSTTL loads of 10 pF each, the CL on the CMOS gate output would be 10 * 10 = 100 pF. Since the CMOS gate timing is specified at CL =150 pF, there is only 150-100 = 50 pF left over to drive the additional CMOS loads. Since the CMOS Cin is 25 pF, the number of additional gates that can be driven is:

50 pF/25 pF = (remaining CL) / (Cin of additional CMOS inputs) = 2

Practically speaking, the wiring capacitance on a PC board will generally be in the 2–3 pF per inch range, so allowing 25 pF for wiring capacitance would permit one CMOS load in addition to the 10 LSTTL loads from above.

What if the CMOS output were to drive only CMOS loads? The input capacitance of the CMOS gate is 25 pF, so even if all loads were CMOS, it can only drive CL/Cin = 150 pF / 25 pF = 6 CMOS loads, and still meet its test condition limits. Since we must also allow for the wiring capacitance, we should limit this device to five loads, leaving 25 pF for the wiring capacitance. The additional load capacitance from more than five devices would likely result in timing performance that would be poorer than that specified in the data sheet. Excessive capacitance can also make ground bounce worse, which is the change in on-chip ground voltage due to rapid current spikes caused by charging load capacitance, developing a voltage across the lead inductance of the driving IC.

Transmission Line Effects

When using high-speed logic and the rise and fall times are of the same order as the propagation of the signal, transmission line effects become significant. When a signal transition propagates down a wire, it will be reflected back if the signal is not absorbed at the destination end. At lower speeds, the effect can be ignored, but with the fastest processors now in use, most designers will

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need to consider whether the effects will have a negative impact on their designs, and take appropriate action if necessary.

There are several characteristics of digital transmission lines that must be addressed, including the following:

•signal transition time vs. clock rate

•mutual inductance and capacitance (crosstalk)

•physical layout effects

•impedance estimates

•strip line vs. micro strip

•effects of unmatched impedances

•termination and other alternatives

•series termination vs. parallel termination

•DC vs. AC termination techniques

The techniques for high speed design are beyond the scope of this text, and are covered in detail in an excellent text on the subject, High Speed Digital Design, a Handbook of Black Magic, by Howard W. Johnson and Martin Graham. In contrast with the subtitle, this subject is easily understood by applying some very basic physics.

A transmission line is a conductor long enough so that the signal at the far end of the line is significantly different from the near end, due to the time it takes the signal to propagate from one end to the other.

In this book, we will assume that the interconnections between the devices are not long enough to require transmission line analysis. In order to verify that this is the case we can use a simple estimate. The rough estimate we will make is based on the idea that a wire does not have to be analyzed as a transmission line if the signal takes longer to rise or fall than it takes to get from one end of the wire to another. In other words, if the signal doesn’t have to travel too far, both ends of the wire are at approximately the same voltage. In order to come up with a numerical value to determine if a signal must be treated as a transmission line, there is a simple calculation that can be used, shown below.

l = Tr / D, where

l = length of rising or falling edge in inches (in) Tr = rise time in picoseconds (pS)

D = delay in picoseconds per inch (pS/in)